SN74LVC112ADBR
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Lifecycle Status | ACTIVE (Last Updated: 4 days ago) |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 16-SSOP (0.209, 5.30mm Width) |
| Number of Pins | 16 |
| Weight | 128.593437mg |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Cut Tape (CT) |
| Series | 74LVC |
| JESD-609 Code | e4 |
| Pbfree Code | yes |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 16 |
| ECCN Code | EAR99 |
| Type | JK Type |
| Terminal Finish | Nickel/Palladium/Gold (Ni/Pd/Au) |
| Subcategory | FF/Latches |
| Packing Method | TR |
| Technology | CMOS |
| Voltage - Supply | 1.65V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 1.8V |
| Terminal Pitch | 0.65mm |
| Base Part Number | 74LVC112 |
| Function | Set(Preset) and Reset |
| Output Type | Differential |
| Polarity | Non-Inverting |
| Supply Voltage-Min (Vsup) | 2V |
| Number of Circuits | 2 |
| Load Capacitance | 50pF |
| Output Current | 24mA |
| Clock Frequency | 150MHz |
| Propagation Delay | 7.1 ns |
| Turn On Delay Time | 1 ns |
| Family | LVC/LCX/Z |
| Logic Function | AND, Flip-Flop, JK-Type |
| Current - Quiescent (Iq) | 10μA |
| Current - Output High, Low | 24mA 24mA |
| Number of Bits per Element | 1 |
| Max Propagation Delay @ V, Max CL | 5.9ns @ 3.3V, 50pF |
| Prop. Delay@Nom-Sup | 4.8 ns |
| Trigger Type | Negative Edge |
| Input Capacitance | 4.5pF |
| Schmitt Trigger | No |
| Number of Input Lines | 3 |
| Clock Edge Trigger Type | Negative Edge |
| Height | 2mm |
| Length | 6.2mm |
| Width | 5.3mm |
| Thickness | 1.95mm |
| Radiation Hardening | No |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
SN74LVC112ADBR Overview
It is embeded in 16-SSOP (0.209, 5.30mm Width) case. You can find it in the Cut Tape (CT)package. As configured, the output uses Differential. The trigger configured with it uses Negative Edge. Surface Mountis positioned in the way of this electronic part. It operates with a supply voltage of 1.65V~3.6V. -40°C~85°C TAis the operating temperature. JK Typedescribes this flip flop. FPGAs belonging to the 74LVCseries contain this type of chip. Its output frequency should not exceed 150MHz. This process consumes 10μA quiescents. In 16terminations, a transmission line is terminated with a JK flip flop that matches its characteristic impedance. The 74LVC112 family contains it. An input voltage of 1.8Vpowers the D latch. A 4.5pFfarad input capacitance is provided by this T flip flop. Devices in the LVC/LCX/Zfamily are electronic devices. In this case, the electronic component is mounted in the way of Surface Mount. Basically, it is designed with a set of 16 pins. The clock edge trigger type for this device is Negative Edge. The part you are looking for is included in FF/Latches. For normal operation, the supply voltage (Vsup) should be above 2V. The superior flexibility is achieved through the use of 2 circuits. In view of its reliability, this D flip flop is a good fit for TR. Its output current of 24mAallows for maximum design flexibility. This input has 3lines in it.
SN74LVC112ADBR Features
Cut Tape (CT) package
74LVC series
16 pins
SN74LVC112ADBR Applications
There are a lot of Texas Instruments SN74LVC112ADBR Flip Flops applications.
- Asynchronous counter
- Bounce elimination switch
- Buffered Clock
- ESD protection
- Bus hold
- Power down protection
- Patented noise
- Dynamic threshold performance
- Reduced system switching noise
- 2 – Bit synchronous counter
