SN74LVC112APWT
| Parameters | |
|---|---|
| Series | 74LVC |
| JESD-609 Code | e4 |
| Pbfree Code | yes |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 16 |
| Termination | SMD/SMT |
| Type | JK Type |
| Terminal Finish | Nickel/Palladium/Gold (Ni/Pd/Au) |
| Subcategory | FF/Latches |
| Packing Method | TR |
| Technology | CMOS |
| Voltage - Supply | 1.65V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 1.8V |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| Base Part Number | 74LVC112 |
| Function | Set(Preset) and Reset |
| Qualification Status | Not Qualified |
| Output Type | Differential |
| Polarity | Non-Inverting |
| Supply Voltage-Min (Vsup) | 2V |
| Number of Circuits | 2 |
| Load Capacitance | 50pF |
| Output Current | 24mA |
| Clock Frequency | 150MHz |
| Propagation Delay | 7.1 ns |
| Turn On Delay Time | 1 ns |
| Family | LVC/LCX/Z |
| Logic Function | AND, Flip-Flop, JK-Type |
| Current - Quiescent (Iq) | 10μA |
| Current - Output High, Low | 24mA 24mA |
| Number of Bits per Element | 1 |
| Max Propagation Delay @ V, Max CL | 5.9ns @ 3.3V, 50pF |
| Prop. Delay@Nom-Sup | 4.8 ns |
| Trigger Type | Negative Edge |
| Input Capacitance | 4.5pF |
| Schmitt Trigger | No |
| Number of Input Lines | 3 |
| Clock Edge Trigger Type | Negative Edge |
| Height | 1.2mm |
| Length | 5mm |
| Width | 4.4mm |
| Thickness | 1mm |
| REACH SVHC | No SVHC |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
| Factory Lead Time | 1 Week |
| Lifecycle Status | ACTIVE (Last Updated: 1 day ago) |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 16-TSSOP (0.173, 4.40mm Width) |
| Number of Pins | 16 |
| Weight | 61.887009mg |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tape & Reel (TR) |
SN74LVC112APWT Overview
As a result, it is packaged as 16-TSSOP (0.173, 4.40mm Width). The package Tape & Reel (TR)contains it. There is a Differentialoutput configured with it. This trigger is configured to use Negative Edge. It is mounted in the way of Surface Mount. With a supply voltage of 1.65V~3.6V volts, it operates. The operating temperature is -40°C~85°C TA. It belongs to the type JK Typeof flip flops. It belongs to the 74LVCseries of FPGAs. It should not exceed 150MHzin its output frequency. It consumes 10μA of quiescent current without being affected by external factors. There have been 16 terminations. This D latch belongs to the family of 74LVC112. The power supply voltage is 1.8V. The input capacitance of this T flip flop is 4.5pF farads, which is defined as the capacitance between the input terminals of an op amp with either input grounded. This D flip flop belongs to the family of LVC/LCX/Z. A part of the electronic system is mounted in the way of Surface Mount. This board is designed with 16pins on it. This device exhibits a clock edge trigger type of Negative Edge. The part you are looking for is included in FF/Latches. For normal operation, the supply voltage (Vsup) should be kept above 2V. Due to its superior flexibility, it uses 2 circuits. Compared to other similar T flip flops, this device offers reliable performance and is well suited for TR. As a result of its output current of 24mA, it is very flexible in terms of design. A total of 3input lines have been provided.
SN74LVC112APWT Features
Tape & Reel (TR) package
74LVC series
16 pins
SN74LVC112APWT Applications
There are a lot of Texas Instruments SN74LVC112APWT Flip Flops applications.
- 2 – Bit synchronous counter
- Test & Measurement
- Memory
- Individual Asynchronous Resets
- Modulo – n – counter
- Data transfer
- ESD protection
- Parallel data storage
- Dynamic threshold performance
- Bounce elimination switch
