SN74LVTH374IPWREP
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Lifecycle Status | ACTIVE (Last Updated: 5 days ago) |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 20-TSSOP (0.173, 4.40mm Width) |
| Number of Pins | 20 |
| Weight | 76.997305mg |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74LVTH |
| JESD-609 Code | e4 |
| Pbfree Code | yes |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 20 |
| ECCN Code | EAR99 |
| Type | D-Type |
| Terminal Finish | Nickel/Palladium/Gold (Ni/Pd/Au) |
| Subcategory | FF/Latches |
| Packing Method | TR |
| Technology | CMOS |
| Voltage - Supply | 2.7V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 3.3V |
| Terminal Pitch | 0.65mm |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| Base Part Number | 74LVTH374 |
| Function | Standard |
| Qualification Status | Not Qualified |
| Output Type | Tri-State, Non-Inverted |
| Operating Supply Voltage | 3.3V |
| Number of Elements | 1 |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 3.6V |
| Supply Voltage-Min (Vsup) | 2.7V |
| Load Capacitance | 50pF |
| Number of Ports | 2 |
| Output Current | 64mA |
| Number of Bits | 8 |
| Clock Frequency | 150MHz |
| Propagation Delay | 2.9 ns |
| Turn On Delay Time | 2.9 ns |
| Family | LVT |
| Current - Quiescent (Iq) | 190μA |
| Output Characteristics | 3-STATE |
| Current - Output High, Low | 32mA 64mA |
| Max I(ol) | 0.064 A |
| Max Propagation Delay @ V, Max CL | 4.5ns @ 3.3V, 50pF |
| Prop. Delay@Nom-Sup | 4.5 ns |
| Trigger Type | Positive Edge |
| Input Capacitance | 3pF |
| Power Supply Current-Max (ICC) | 5mA |
| Number of Output Lines | 8 |
| Count Direction | UNIDIRECTIONAL |
| Clock Edge Trigger Type | Positive Edge |
| Translation | N/A |
| Height | 1.2mm |
| Length | 6.5mm |
| Width | 4.4mm |
| Thickness | 1mm |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
SN74LVTH374IPWREP Overview
As a result, it is packaged as 20-TSSOP (0.173, 4.40mm Width). The package Tape & Reel (TR)contains it. As configured, the output uses Tri-State, Non-Inverted. It is configured with the trigger Positive Edge. There is an electric part mounted in the way of Surface Mount. The JK flip flop operates at a voltage of 2.7V~3.6V. A temperature of -40°C~85°C TAis used in the operation. The type of this D latch is D-Type. In FPGA terms, D flip flop is a type of 74LVTHseries FPGA. A frequency of 150MHzshould not be exceeded by its output. In total, there are 1 elements. There is 190μA quiescent consumption. There are 20 terminations,This D latch belongs to the family of 74LVTH374. A voltage of 3.3V provides power to the D latch. A 3pFfarad input capacitance is provided by this T flip flop. This D flip flop belongs to the family of LVT. A part of the electronic system is mounted in the way of Surface Mount. This board is designed with 20pins on it. The clock edge trigger type for this device is Positive Edge. It is part of the FF/Latchesbase part number family. The design is based on 8bits. As soon as 3.6Vis reached, Vsup reaches its maximum value. Normal operation requires a supply voltage (Vsup) above 2.7V. Considering the reliability of this T flip flop, it is well suited for TR. This D flip flop is equipped with 0 ports. High efficiency requires the supply voltage to be maintained at 3.3V. As a result of its output current of 64mA, it is very flexible in terms of design. To operate, the chip has a total of 8 output lines.
SN74LVTH374IPWREP Features
Tape & Reel (TR) package
74LVTH series
20 pins
8 Bits
SN74LVTH374IPWREP Applications
There are a lot of Texas Instruments SN74LVTH374IPWREP Flip Flops applications.
- Frequency division
- Data storage
- Buffer registers
- Computing
- Storage Registers
- High Performance Logic for test systems
- Counters
- Registers
- Count Modes
- Synchronous counter
