SN74S112AN
| Parameters | |
|---|---|
| Number of Circuits | 2 |
| Output Current | 20mA |
| Clock Frequency | 125MHz |
| Propagation Delay | 7 ns |
| Turn On Delay Time | 4 ns |
| Family | S |
| Logic Function | Flip-Flop |
| Current - Quiescent (Iq) | 252mA |
| Current - Output High, Low | 1mA 20mA |
| Number of Bits per Element | 1 |
| Max Propagation Delay @ V, Max CL | 7ns @ 5V, 50pF |
| Trigger Type | Negative Edge |
| Schmitt Trigger | No |
| Power Supply Current-Max (ICC) | 6mA |
| Number of Input Lines | 5 |
| Clock Edge Trigger Type | Negative Edge |
| Max Frequency@Nom-Sup | 80000000Hz |
| Height | 5.08mm |
| Length | 19.3mm |
| Width | 6.35mm |
| Thickness | 3.9mm |
| Radiation Hardening | No |
| REACH SVHC | No SVHC |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
| Factory Lead Time | 1 Week |
| Lifecycle Status | ACTIVE (Last Updated: 1 day ago) |
| Mount | Through Hole |
| Mounting Type | Through Hole |
| Package / Case | 16-DIP (0.300, 7.62mm) |
| Number of Pins | 16 |
| Weight | 951.693491mg |
| Operating Temperature | 0°C~70°C TA |
| Packaging | Tube |
| Series | 74S |
| JESD-609 Code | e4 |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 16 |
| ECCN Code | EAR99 |
| Type | JK Type |
| Terminal Finish | Nickel/Palladium/Gold (Ni/Pd/Au) |
| Subcategory | FF/Latches |
| Technology | TTL |
| Voltage - Supply | 4.75V~5.25V |
| Terminal Position | DUAL |
| Supply Voltage | 5V |
| Base Part Number | 74S112 |
| Function | Set(Preset) and Reset |
| Output Type | Differential |
| Operating Supply Voltage | 5V |
| Polarity | Non-Inverting |
| Power Supplies | 5V |
SN74S112AN Overview
16-DIP (0.300, 7.62mm)is the packaging method. A package named Tubeincludes it. It is configured with Differentialas an output. JK flip flop uses Negative Edgeas the trigger. In this case, the electronic component is mounted in the way of Through Hole. A voltage of 4.75V~5.25Vis used as the supply voltage. Temperature is set to 0°C~70°C TA. This logic flip flop is classified as type JK Type. It is a type of FPGA belonging to the 74S series. A frequency of 125MHzshould be the maximum output frequency. As a result, it consumes 252mA of quiescent current without being affected by external factors. There have been 16 terminations. The 74S112 family contains this object. An input voltage of 5Vpowers the D latch. Devices in the Sfamily are electronic devices. Electronic part Through Holeis mounted in the way. The electronic flip flop is designed with pins 16. Its clock edge trigger type is Negative Edge. This RS flip flops is a part number FF/Latches. The superior flexibility of this circuit is achieved by using 2 circuits. The D latch operates on 5V volts. High efficiency requires the supply voltage to be maintained at 5V. The output current of 20mA makes it feature maximum design flexibility. This input has 5lines.
SN74S112AN Features
Tube package
74S series
16 pins
5V power supplies
SN74S112AN Applications
There are a lot of Texas Instruments SN74S112AN Flip Flops applications.
- Parallel data storage
- Single Down Count-Control Line
- Common Clocks
- Single Up Count-Control Line
- Buffered Clock
- Frequency Divider circuits
- Digital electronics systems
- Reduced system switching noise
- Memory
- Communications
