Parameters | |
---|---|
ECCN Code | EAR99 |
Terminal Finish | Nickel/Palladium/Gold (Ni/Pd/Au) |
Max Power Dissipation | 238mW |
Technology | CMOS |
Terminal Position | DUAL |
Terminal Form | GULL WING |
Supply Voltage | 3.3V |
Frequency | 16MHz |
Base Part Number | STM8S003 |
Pin Count | 20 |
Interface | I2C, IrDA, LIN, SPI, UART |
Memory Size | 8kB |
Oscillator Type | Internal |
Number of I/O | 16 |
RAM Size | 1K x 8 |
Voltage - Supply (Vcc/Vdd) | 2.95V~5.5V |
uPs/uCs/Peripheral ICs Type | MICROCONTROLLER |
Core Processor | STM8 |
Peripherals | Brown-out Detect/Reset, POR, PWM, WDT |
Program Memory Type | FLASH |
Core Size | 8-Bit |
Program Memory Size | 8KB 8K x 8 |
Connectivity | I2C, IrDA, LINbus, SPI, UART/USART |
Bit Size | 8 |
Data Converter | A/D 5x10b |
Watchdog Timer | Yes |
Has ADC | YES |
DMA Channels | NO |
Data Bus Width | 8b |
PWM Channels | YES |
Number of Timers/Counters | 3 |
EEPROM Size | 128 x 8 |
On Chip Program ROM Width | 8 |
Boundary Scan | NO |
Low Power Mode | YES |
Format | FIXED-POINT |
Integrated Cache | NO |
Number of ADC Channels | 5 |
Max Junction Temperature (Tj) | 150°C |
Number of External Interrupts | 16 |
On Chip Data RAM Width | 8 |
Ambient Temperature Range High | 85°C |
Number of SPI Channels | 1 |
Height | 1.2mm |
Radiation Hardening | No |
RoHS Status | ROHS3 Compliant |
Lead Free | Lead Free |
Factory Lead Time | 1 Week |
Lifecycle Status | ACTIVE (Last Updated: 6 months ago) |
Mount | Surface Mount |
Mounting Type | Surface Mount |
Package / Case | 20-TSSOP (0.173, 4.40mm Width) |
Number of Pins | 20 |
Operating Temperature | -40°C~85°C TA |
Packaging | Tape & Reel (TR) |
Series | STM8S |
JESD-609 Code | e4 |
Part Status | Active |
Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
Number of Terminations | 20 |
The STM8S003F3P6TR value line 8-bit microcontrollers offer 8 Kbytes of Flash program
memory, plus integrated true data EEPROM. They are referred to as low-density devices in
the STM8S microcontroller family reference manual (RM0016).
16 MHz advanced STM8 core with Harvard
architecture and 3-stage pipeline
Extended instruction set