TC7WH74FU,LJ(CT
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 8-TSSOP, 8-MSOP (0.110, 2.80mm Width) |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Cut Tape (CT) |
| Published | 2009 |
| Series | TC7WH |
| Pbfree Code | yes |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 8 |
| Type | D-Type |
| Technology | CMOS |
| Voltage - Supply | 2V~5.5V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | NOT SPECIFIED |
| Supply Voltage | 3.3V |
| Terminal Pitch | 0.65mm |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| Base Part Number | 7WH74 |
| JESD-30 Code | R-PDSO-G8 |
| Function | Set(Preset) and Reset |
| Output Type | Differential |
| Number of Elements | 1 |
| Supply Voltage-Max (Vsup) | 5.5V |
| Supply Voltage-Min (Vsup) | 2V |
| Number of Bits | 1 |
| Clock Frequency | 115MHz |
| Propagation Delay | 9.3 ns |
| Quiescent Current | 2μA |
| Family | LV/LV-A/LVX/H |
| Logic Function | AND |
| Current - Output High, Low | 8mA 8mA |
| Output Polarity | COMPLEMENTARY |
| Max Propagation Delay @ V, Max CL | 9.3ns @ 5V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 4pF |
| Clock Edge Trigger Type | Positive Edge |
| Length | 2.9mm |
| Width | 2.8mm |
| RoHS Status | RoHS Compliant |
TC7WH74FU,LJ(CT Overview
8-TSSOP, 8-MSOP (0.110, 2.80mm Width)is the way it is packaged. D flip flop is included in the Cut Tape (CT)package. The output it is configured with uses Differential. In the configuration of the trigger, Positive Edgeis used. Surface Mountis occupied by this electronic component. The JK flip flop operates at a voltage of 2V~5.5V. A temperature of -40°C~85°C TAis considered to be the operating temperature. D-Typedescribes this flip flop. It belongs to the TC7WHseries of FPGAs. Its output frequency should not exceed 115MHz Hz. A total of 1 elements are present. It has been determined that there have been 8 terminations. Members of the 7WH74family make up this object. A voltage of 3.3V is used as the power supply for this D latch. JK flip flop input capacitance is 4pF farads. Devices in the LV/LV-A/LVX/Hfamily are electronic devices. In this case, the electronic component is mounted in the way of Surface Mount. This device's clock edge trigger type is Positive Edge. It is designed with a number of bits of 1. Vsup reaches 5.5V, the maximal supply voltage. Normal operation requires a supply voltage (Vsup) above 2V. It consumes 2μA current.
TC7WH74FU,LJ(CT Features
Cut Tape (CT) package
TC7WH series
1 Bits
TC7WH74FU,LJ(CT Applications
There are a lot of Toshiba Semiconductor and Storage TC7WH74FU,LJ(CT Flip Flops applications.
- Parallel data storage
- Data transfer
- Power down protection
- Load Control
- High Performance Logic for test systems
- Pattern generators
- 2 – Bit synchronous counter
- Modulo – n – counter
- ESD protection
- Patented noise
