Parameters |
Number of Macro Cells |
128 |
JTAG BST |
YES |
In-System Programmable |
YES |
Height Seated (Max) |
1.2mm |
Length |
5mm |
Width |
5mm |
RoHS Status |
RoHS Compliant |
Mount |
Surface Mount |
Package / Case |
TFBGA |
Number of Pins |
68 |
JESD-609 Code |
e0 |
Pbfree Code |
no |
Number of Terminations |
68 |
Terminal Finish |
TIN LEAD |
Max Operating Temperature |
85°C |
Min Operating Temperature |
0°C |
Additional Feature |
YES |
HTS Code |
8542.39.00.01 |
Subcategory |
Programmable Logic Devices |
Technology |
CMOS |
Terminal Position |
BOTTOM |
Terminal Form |
BALL |
Peak Reflow Temperature (Cel) |
235 |
Supply Voltage |
1.8V |
Terminal Pitch |
0.5mm |
Time@Peak Reflow Temperature-Max (s) |
30 |
Pin Count |
68 |
Qualification Status |
Not Qualified |
Supply Voltage-Max (Vsup) |
1.89V |
Power Supplies |
1.2/3.31.8V |
Temperature Grade |
OTHER |
Supply Voltage-Min (Vsup) |
1.71V |
Number of I/O |
52 |
Clock Frequency |
184.1MHz |
Propagation Delay |
7.9 ns |
Programmable Logic Type |
FLASH PLD |
Number of Logic Blocks (LABs) |
160 |
Output Function |
MACROCELL |
5M160ZM68C4 Overview
There are 128 macro cells. A macro cell is a cell in a mobile phone network that provides radio coverage through the use of a high-power cell site (tower, antenna or mast).It is part of the TFBGA package.The device has 52inputs and outputs.68terminations are programmed into the device.This electrical part has a terminal position of [0], which serves as an important point of access for passengers and freight.The power supply voltage is 1.8V.It is included in Programmable Logic Devices.With 68pins programmed, the chip is ready to use.When using this device, YESis also available.In this case, Surface Mountis used to mount the electronic component.The device has a pinout of [0].The system runs on a power supply of 1.2/3.31.8V watts.The maximal supply voltage (Vsup) reaches 1.89V.In order to operate, the temperature should be higher than 0°C.It is recommended that the operating temperature be below 85°C.Its basic building block is composed of 160 logic blocks (LABs).There should be a higher supply voltage (Vsup) than 1.71V.It should not exceed 184.1MHzin terms of clockfrequency.Programmable logic types can be divided into FLASH PLD.
5M160ZM68C4 Features
TFBGA package
52 I/Os
68 pin count
68 pins
1.2/3.31.8V power supplies
160 logic blocks (LABs)
5M160ZM68C4 Applications
There are a lot of Altera 5M160ZM68C4 CPLDs applications.
- Address decoding
- Address decoders
- Code converters
- Auxiliary Power Supply Isolated and Non-isolated
- Multiple Clock Source Selection
- Network Interface Card (NIC) and Host Bus Adapter (HBA)
- ToR/Aggregation/Core Switch and Router
- Reset swapping
- SUPERVISORY FUNCTION (LVD AND WATCHDOG)
- Power automation