Parameters |
Min Operating Temperature |
-40°C |
Additional Feature |
YES |
HTS Code |
8542.39.00.01 |
Subcategory |
Programmable Logic Devices |
Technology |
CMOS |
Terminal Position |
BOTTOM |
Terminal Form |
BALL |
Peak Reflow Temperature (Cel) |
NOT SPECIFIED |
Supply Voltage |
1.8V |
Terminal Pitch |
0.5mm |
Time@Peak Reflow Temperature-Max (s) |
NOT SPECIFIED |
Pin Count |
68 |
Qualification Status |
Not Qualified |
Supply Voltage-Max (Vsup) |
1.89V |
Power Supplies |
1.81.2/3.3V |
Temperature Grade |
INDUSTRIAL |
Supply Voltage-Min (Vsup) |
1.71V |
Number of I/O |
52 |
Clock Frequency |
118.3MHz |
Propagation Delay |
14 ns |
Programmable Logic Type |
FLASH PLD |
Number of Logic Blocks (LABs) |
80 |
Output Function |
MACROCELL |
Number of Macro Cells |
64 |
JTAG BST |
YES |
In-System Programmable |
YES |
Height Seated (Max) |
1.2mm |
Length |
5mm |
Width |
5mm |
RoHS Status |
RoHS Compliant |
Mount |
Surface Mount |
Package / Case |
TFBGA |
Number of Pins |
68 |
JESD-609 Code |
e0 |
Pbfree Code |
no |
Number of Terminations |
68 |
Terminal Finish |
TIN LEAD |
Max Operating Temperature |
100°C |
5M80ZM68I5 Overview
There are 64 macro cells. A macro cell is a cell in a mobile phone network that provides radio coverage through the use of a high-power cell site (tower, antenna or mast).It is embedded in the TFBGA package.This device has 52 I/O ports programmed into it.There are 68 terminations programmed into the device.This electrical component has a terminal position of 0.A voltage of 1.8Vprovides power to the device.This part is in the family [0].It is equipped with 68 pin count.When using this device, YEScan also be found.Surface Mountmounts this electronic component.68pins are included in its design.The system runs on a power supply of 1.81.2/3.3V watts.Supply voltage (Vsup) reaches a maximum of 1.89V.Ideally, the operating temperature should be greater than -40°C.A temperature lower than 100°Cis recommended for operation.In its simplest form, it consists of 80 logic blocks (LABs).Vsup (supply voltage) must be greater than 1.71V.The clock frequency of this device should not exceed 118.3MHz.A programmable logic type can be categorized as FLASH PLD.
5M80ZM68I5 Features
TFBGA package
52 I/Os
68 pin count
68 pins
1.81.2/3.3V power supplies
80 logic blocks (LABs)
5M80ZM68I5 Applications
There are a lot of Altera 5M80ZM68I5 CPLDs applications.
- Network Interface Card (NIC) and Host Bus Adapter (HBA)
- DMA control
- ON-CHIP OSCILLATOR CIRCUIT
- Software Configuration of Add-In Boards
- Configurable Addressing of I/O Boards
- SFP, QSFP, QSFP-DD, OSFP, Mini-SAS HD Port Management
- TIMERS/COUNTERS
- PLC analog input modules
- High speed graphics processing
- Cross-Matrix Switch