74ABT16823ADGG,118
| Parameters | |
|---|---|
| Mounting Type | Surface Mount |
| Package / Case | 56-TFSOP (0.240, 6.10mm Width) |
| Surface Mount | YES |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74ABT |
| JESD-609 Code | e4 |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 56 |
| Type | D-Type |
| Terminal Finish | NICKEL PALLADIUM GOLD |
| Additional Feature | WITH CLEAR AND CLOCK ENABLE |
| Technology | BICMOS |
| Voltage - Supply | 4.5V~5.5V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 5V |
| Terminal Pitch | 0.5mm |
| Reach Compliance Code | unknown |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | 74ABT16823 |
| JESD-30 Code | R-PDSO-G56 |
| Function | Master Reset |
| Qualification Status | Not Qualified |
| Output Type | Tri-State, Non-Inverted |
| Number of Elements | 2 |
| Supply Voltage-Max (Vsup) | 5.5V |
| Supply Voltage-Min (Vsup) | 4.5V |
| Number of Ports | 2 |
| Clock Frequency | 190MHz |
| Family | ABT |
| Current - Quiescent (Iq) | 1mA |
| Output Characteristics | 3-STATE |
| Current - Output High, Low | 32mA 64mA |
| Output Polarity | TRUE |
| Number of Bits per Element | 9 |
| Max Propagation Delay @ V, Max CL | 3.2ns @ 5V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 4pF |
| Length | 14mm |
| Width | 6.1mm |
| RoHS Status | ROHS3 Compliant |
74ABT16823ADGG,118 Overview
The item is packaged in 56-TFSOP (0.240, 6.10mm Width)cases. Package Tape & Reel (TR)embeds it. In the configuration, Tri-State, Non-Invertedis used as the output. It is configured with a trigger that uses Positive Edge. There is an electrical part that is mounted in the way of Surface Mount. A voltage of 4.5V~5.5Vis required for its operation. It is operating at a temperature of -40°C~85°C TA. There is D-Type type of electronic flip flop associated with this device. In FPGA terms, D flip flop is a type of 74ABTseries FPGA. It should not exceed 190MHzin terms of its output frequency. D latch consists of 2 elements. Despite external influences, it consumes 1mAof quiescent current. There are 56 terminations,If you search by 74ABT16823, you will find similar parts. A voltage of 5V is used as the power supply for this D latch. Input capacitance of this device is 4pF farads. In this case, the D flip flop belongs to the ABTfamily. As soon as Vsup reaches 5.5V, the maximum supply voltage is reached. Normal operation requires a supply voltage (Vsup) above 4.5V. The D flip flop has no ports embedded. Furthermore, it has WITH CLEAR AND CLOCK ENABLEas a characteristic.
74ABT16823ADGG,118 Features
Tape & Reel (TR) package
74ABT series
74ABT16823ADGG,118 Applications
There are a lot of NXP USA Inc. 74ABT16823ADGG,118 Flip Flops applications.
- Synchronous counter
- ESCC
- Matched Rise and Fall
- Balanced Propagation Delays
- Storage registers
- Convert a momentary switch to a toggle switch
- Communications
- Reduced system switching noise
- Power down protection
- Divide a clock signal by 2 or 4
