74ALVC374D,118
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 20-SOIC (0.295, 7.50mm Width) |
| Number of Pins | 20 |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74ALVC |
| JESD-609 Code | e4 |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 20 |
| Type | D-Type |
| Terminal Finish | Nickel/Palladium/Gold (Ni/Pd/Au) |
| Technology | CMOS |
| Voltage - Supply | 1.65V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 2.7V |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | 74ALVC374 |
| Function | Standard |
| Output Type | Tri-State, Non-Inverted |
| Number of Elements | 1 |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 3.6V |
| Number of Ports | 2 |
| Output Current | 50mA |
| Number of Bits | 8 |
| Clock Frequency | 300MHz |
| Propagation Delay | 2.5 ns |
| Turn On Delay Time | 3.1 ns |
| Family | ALVC/VCX/A |
| Logic Function | D-Type, Flip-Flop |
| Current - Quiescent (Iq) | 10μA |
| Output Characteristics | 3-STATE |
| Current - Output High, Low | 24mA 24mA |
| Max Propagation Delay @ V, Max CL | 3.6ns @ 3.3V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 3.5pF |
| Number of Output Lines | 8 |
| Clock Edge Trigger Type | Positive Edge |
| Height Seated (Max) | 2.65mm |
| Width | 7.5mm |
| Radiation Hardening | No |
| REACH SVHC | No SVHC |
| RoHS Status | ROHS3 Compliant |
74ALVC374D,118 Overview
The package is in the form of 20-SOIC (0.295, 7.50mm Width). D flip flop is included in the Tape & Reel (TR)package. T flip flop uses Tri-State, Non-Invertedas the output. It is configured with the trigger Positive Edge. Surface Mountmounts this electrical part. It operates with a supply voltage of 1.65V~3.6V. A temperature of -40°C~85°C TAis used in the operation. Logic flip flops of this type are classified as D-Type. In FPGA terms, D flip flop is a type of 74ALVCseries FPGA. Its output frequency should not exceed 300MHz. A total of 1 elements are present. Despite external influences, it consumes 10μAof quiescent current. The number of terminations is 20. The 74ALVC374family includes it. An input voltage of 2.7Vpowers the D latch. There is 3.5pF input capacitance for this T flip flop. This D flip flop belongs to the family of ALVC/VCX/A. A part of the electronic system is mounted in the way of Surface Mount. The electronic flip flop is designed with pins 20. This device has Positive Edgeas its clock edge trigger type. There are 8bits in this flip flop. As soon as Vsup reaches 3.6V, the maximum supply voltage is reached. A total of 2ports are embedded in the D flip flop. The output current of 50mA makes it feature maximum design flexibility. The JK flip flop is with 8 output lines to operate.
74ALVC374D,118 Features
Tape & Reel (TR) package
74ALVC series
20 pins
8 Bits
74ALVC374D,118 Applications
There are a lot of Nexperia USA Inc. 74ALVC374D,118 Flip Flops applications.
- Patented noise
- Latch
- Divide a clock signal by 2 or 4
- Frequency Divider circuits
- Computing
- Digital electronics systems
- Memory
- Common Clocks
- Asynchronous counter
- Power down protection
