74AUP1G80GS,132
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 6-XFDFN |
| Number of Pins | 6 |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74AUP |
| JESD-609 Code | e3 |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 6 |
| Type | D-Type |
| Terminal Finish | Tin (Sn) |
| Technology | CMOS |
| Voltage - Supply | 0.8V~3.6V |
| Terminal Position | DUAL |
| Supply Voltage | 1.1V |
| Terminal Pitch | 0.35mm |
| Base Part Number | 74AUP1G80 |
| Function | Standard |
| Output Type | Inverted |
| Number of Elements | 1 |
| Polarity | Inverting |
| Supply Voltage-Min (Vsup) | 0.8V |
| Output Current | 20mA |
| Number of Bits | 1 |
| Clock Frequency | 309MHz |
| Propagation Delay | 15.7 ns |
| Quiescent Current | 500nA |
| Turn On Delay Time | 2.2 ns |
| Family | AUP/ULP/V |
| Current - Output High, Low | 4mA 4mA |
| Max Propagation Delay @ V, Max CL | 6.4ns @ 3.3V, 30pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 1.5pF |
| Clock Edge Trigger Type | Positive Edge |
| Height Seated (Max) | 0.35mm |
| Radiation Hardening | No |
| REACH SVHC | No SVHC |
| RoHS Status | ROHS3 Compliant |
74AUP1G80GS,132 Overview
6-XFDFNis the way it is packaged. The Tape & Reel (TR)package contains it. The output it is configured with uses Inverted. The trigger configured with it uses Positive Edge. This electronic part is mounted in the way of Surface Mount. A voltage of 0.8V~3.6Vis required for its operation. It is at -40°C~125°C TAdegrees Celsius that the system is operating. D-Typedescribes this flip flop. The FPGA belongs to the 74AUP series. Its output frequency should not exceed 309MHz Hz. In total, it contains 1 elements. There are 6 terminations, which are the practice of ending a transmission line with a device that matches the characteristic impedance of the line. The object belongs to the 74AUP1G80 family. Power is supplied from a voltage of 1.1V volts. Its input capacitance is 1.5pF farads. Electronic devices of this type belong to the AUP/ULP/Vfamily. Electronic part Surface Mountis mounted in the way. A total of 6pins are provided on this board. A Positive Edgeclock edge trigger is used in this device. The flip flop is designed with 1bits. If you want to maintain normal operation, you should keep the supply voltage (Vsup) above 0.8V. The 20mA output current allows it to be designed with the greatest amount of flexibility. Quiescent current is consumed by the D latch in the amount of 500nA.
74AUP1G80GS,132 Features
Tape & Reel (TR) package
74AUP series
6 pins
1 Bits
74AUP1G80GS,132 Applications
There are a lot of Nexperia USA Inc. 74AUP1G80GS,132 Flip Flops applications.
- Circuit Design
- Matched Rise and Fall
- Parallel data storage
- Shift Registers
- CMOS Process
- Shift registers
- Computing
- Storage registers
- Divide a clock signal by 2 or 4
- Frequency Divider circuits
