Parameters |
Factory Lead Time |
1 Week |
Lifecycle Status |
ACTIVE (Last Updated: 2 days ago) |
Contact Plating |
Tin |
Mount |
Surface Mount |
Mounting Type |
Surface Mount |
Package / Case |
20-SOIC (0.295, 7.50mm Width) |
Number of Pins |
20 |
Weight |
801mg |
Operating Temperature |
-40°C~85°C TA |
Packaging |
Tube |
Series |
74LVT |
JESD-609 Code |
e3 |
Pbfree Code |
yes |
Part Status |
Active |
Moisture Sensitivity Level (MSL) |
1 (Unlimited) |
Number of Terminations |
20 |
Termination |
SMD/SMT |
ECCN Code |
EAR99 |
Type |
D-Type |
Subcategory |
FF/Latches |
Packing Method |
RAIL |
Technology |
BICMOS |
Voltage - Supply |
2.7V~3.6V |
Terminal Position |
DUAL |
Terminal Form |
GULL WING |
Supply Voltage |
3.3V |
Base Part Number |
74LVT574 |
Function |
Standard |
Output Type |
Tri-State, Non-Inverted |
Operating Supply Voltage |
3.3V |
Number of Elements |
1 |
Polarity |
Non-Inverting |
Supply Voltage-Min (Vsup) |
2.7V |
Number of Circuits |
8 |
Load Capacitance |
50pF |
Number of Ports |
2 |
Output Current |
64mA |
Number of Bits |
8 |
Clock Frequency |
150MHz |
Propagation Delay |
5.3 ns |
Turn On Delay Time |
4.5 ns |
Family |
LVT |
Logic Function |
D-Type, Flip-Flop |
Current - Quiescent (Iq) |
190μA |
Number of Inputs |
1 |
Current - Output High, Low |
32mA 64mA |
Max I(ol) |
0.064 A |
Max Propagation Delay @ V, Max CL |
4.6ns @ 3.3V, 50pF |
Trigger Type |
Positive Edge |
Input Capacitance |
4pF |
Number of Output Lines |
3 |
Clock Edge Trigger Type |
Positive Edge |
Height |
2.35mm |
Length |
13mm |
Width |
7.6mm |
Radiation Hardening |
No |
REACH SVHC |
No SVHC |
RoHS Status |
ROHS3 Compliant |
Lead Free |
Lead Free |
74LVT574WM Overview
20-SOIC (0.295, 7.50mm Width)is the packaging method. As part of the package Tube, it is embedded. This output is configured with Tri-State, Non-Inverted. JK flip flop uses Positive Edgeas the trigger. There is an electronic component mounted in the way of Surface Mount. It operates with a supply voltage of 2.7V~3.6V. Temperature is set to -40°C~85°C TA. The type of this D latch is D-Type. JK flip flop is a part of the 74LVTseries of FPGAs. A frequency of 150MHzshould be the maximum output frequency. A total of 1elements are contained within it. During its operation, it consumes 190μA quiescent energy. The number of terminations is 20. The 74LVT574 family contains this object. A voltage of 3.3V is used to power it. A JK flip flop with a 4pFfarad input capacitance is used here. In this case, the D flip flop belongs to the LVTfamily. This electronic part is mounted in the way of Surface Mount. A total of 20pins are provided on this board. There is a clock edge trigger type of Positive Edgeon this device. This device has the base part number FF/Latches. It is designed with a number of bits of 8. Normally, the supply voltage (Vsup) should be above 2.7V. The superior flexibility of this circuit is achieved by using 8 circuits. As a result of its reliability, this D flip flop is ideally suited for RAIL. The flip flop has 2ports embedded within it. For high efficiency, the supply voltage should be kept at 3.3V. With a current output of 64mA , it offers maximum design flexibility. In order for the chip to function, it has 3output lines. 1 inputs are employed.
74LVT574WM Features
Tube package
74LVT series
20 pins
8 Bits
74LVT574WM Applications
There are a lot of ON Semiconductor 74LVT574WM Flip Flops applications.
- Pattern generators
- Asynchronous counter
- Set-reset capability
- Shift registers
- Modulo – n – counter
- Event Detectors
- Buffer registers
- Counters
- 2 – Bit synchronous counter
- Communications