EPM9480RC240-20
| Parameters | |
|---|---|
| Mounting Type | Surface Mount |
| Package / Case | 240-BFQFP Exposed Pad |
| Surface Mount | YES |
| Operating Temperature | 0°C~70°C TA |
| Packaging | Tray |
| Series | MAX® 9000 |
| JESD-609 Code | e0 |
| Pbfree Code | no |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
| Number of Terminations | 240 |
| Terminal Finish | TIN LEAD |
| Additional Feature | 676 FLIP FLOPS; CONFIGURABLE I/O OPERATION WITH 3.3V OR 5V |
| Technology | CMOS |
| Terminal Position | QUAD |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | NOT SPECIFIED |
| Supply Voltage | 5V |
| Terminal Pitch | 0.5mm |
| Reach Compliance Code | unknown |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| Pin Count | 240 |
| JESD-30 Code | S-PQFP-G240 |
| Qualification Status | COMMERCIAL |
| Supply Voltage-Max (Vsup) | 5.25V |
| Supply Voltage-Min (Vsup) | 4.75V |
| Programmable Type | In System Programmable |
| Number of I/O | 175 |
| Clock Frequency | 100MHz |
| Propagation Delay | 23.4 ns |
| Number of Gates | 10000 |
| Output Function | MACROCELL |
| Number of Macro Cells | 480 |
| Voltage Supply - Internal | 4.75V~5.25V |
| Delay Time tpd(1) Max | 20ns |
| Number of Logic Elements/Blocks | 30 |
| Height Seated (Max) | 4.1mm |
| Length | 32mm |
| Width | 32mm |
| RoHS Status | Non-RoHS Compliant |
EPM9480RC240-20 Overview
480 macrocells are present in the mobile phone network, which offer radio coverage from a high-power cell tower, antenna, or mast.It is embedded in the 240-BFQFP Exposed Pad package.There are 175 I/Os programmed in it.The device is programmed with 240 terminations.This electrical part has a terminal position of QUADand is connected to the ground.The power source is powered by 5Vvolts.As a result, it is packaged as Tray.During operation, the operating temperature is kept at 0°C~70°C TA to ensure its reliability.There should be a Surface Mounton the chip.In FPGA terms, it is a type of MAX? 9000series FPGA.The chip is programmed with 240 pins.It is also possible to find 676 FLIP FLOPS; CONFIGURABLE I/O OPERATION WITH 3.3V OR 5Vwhen using this device.A digital circuit can be constructed using 10000gates.There are 30 logic elements/blocks.5.25Vrepresents the maximal supply voltage (Vsup).Vsup (supply voltage) must be greater than 4.75V.It is recommended that the clock frequency not exceed 100MHz.
EPM9480RC240-20 Features
240-BFQFP Exposed Pad package
175 I/Os
The operating temperature of 0°C~70°C TA
240 pin count
EPM9480RC240-20 Applications
There are a lot of Rochester Electronics, LLC EPM9480RC240-20 CPLDs applications.
- Power automation
- Storage Cards and Storage Racks
- State machine control
- LED Lighting systems
- Random logic replacement
- Synchronous or asynchronous mode
- Digital multiplexers
- Address decoding
- Field programmable gate
- Complex programmable logic devices
