MC100EP35MNR4G
| Parameters | |
|---|---|
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 8-VFDFN Exposed Pad |
| Number of Pins | 8 |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tape & Reel (TR) |
| Published | 2008 |
| Series | 100EP |
| Pbfree Code | yes |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 8 |
| Type | JK Type |
| Terminal Finish | Nickel/Gold/Palladium (Ni/Au/Pd) |
| Additional Feature | NECL MODE: VCC = 0V WITH VEE = -3V TO -5.5V |
| Subcategory | FF/Latches |
| Packing Method | TAPE AND REEL |
| Technology | ECL |
| Voltage - Supply | -3V~-5.5V |
| Terminal Position | DUAL |
| Terminal Form | NO LEAD |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 3.3V |
| Terminal Pitch | 0.5mm |
| Time@Peak Reflow Temperature-Max (s) | 40 |
| Base Part Number | 100EP35 |
| Function | Reset |
| Qualification Status | Not Qualified |
| Output Type | Differential |
| Number of Elements | 1 |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 5.5V |
| Power Supplies | -4.5V |
| Supply Voltage-Min (Vsup) | 3V |
| Number of Circuits | 1 |
| Number of Bits | 2 |
| Clock Frequency | 3GHz |
| Propagation Delay | 490 ps |
| Turn On Delay Time | 410 ps |
| Logic Function | Flip-Flop, JK-Type |
| Halogen Free | Halogen Free |
| Prop. Delay@Nom-Sup | 0.575 ns |
| Trigger Type | Positive Edge |
| High Level Output Current | -50mA |
| Low Level Output Current | 50mA |
| Number of Input Lines | 2 |
| Clock Edge Trigger Type | Positive Edge |
| Max Frequency@Nom-Sup | 3000000000Hz |
| RoHS Status | RoHS Compliant |
| Lead Free | Lead Free |
MC100EP35MNR4G Overview
As a result, it is packaged as 8-VFDFN Exposed Pad. You can find it in the Tape & Reel (TR)package. In the configuration, Differentialis used as the output. Positive Edgeis the trigger it is configured with. There is an electric part mounted in the way of Surface Mount. A voltage of -3V~-5.5Vis used as the supply voltage. Temperature is set to -40°C~85°C TA. JK Typeis the type of this D latch. FPGAs belonging to the 100EPseries contain this type of chip. In order for it to function properly, its output frequency should not exceed 3GHz. There are 1 elements in it. A total of 8 terminations have been made. Members of the 100EP35family make up this object. The power supply voltage is 3.3V. In this case, the electronic component is mounted in the way of Surface Mount. The 8pins are designed into the board. The clock edge trigger type for this device is Positive Edge. There is a FF/Latchesbase part number assigned to the RS flip flops. An electronic part designed with 2bits is used in this application. 5.5Vis the maximum supply voltage (Vsup). A normal operating voltage (Vsup) should remain above 3V. Despite its superior flexibility, it relies on 1 circuits to achieve it. Considering the reliability of this T flip flop, it is well suited for TAPE AND REEL. An electrical current of -4.5V volts is applied to it. The number of input lines is 2. Additionally, it is characterized by NECL MODE: VCC = 0V WITH VEE = -3V TO -5.5V. The high level output current is set to -50mA. In the low level output current setting, 50mAis used.
MC100EP35MNR4G Features
Tape & Reel (TR) package
100EP series
8 pins
2 Bits
-4.5V power supplies
MC100EP35MNR4G Applications
There are a lot of ON Semiconductor MC100EP35MNR4G Flip Flops applications.
- Computing
- Latch
- Cold spare funcion
- Digital electronics systems
- Asynchronous counter
- CMOS Process
- Frequency division
- Load Control
- EMI reduction circuitry
- Parallel data storage
