SN74LV174ANSR
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Lifecycle Status | ACTIVE (Last Updated: 1 week ago) |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 16-SOIC (0.209, 5.30mm Width) |
| Number of Pins | 16 |
| Weight | 200.686274mg |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74LV |
| JESD-609 Code | e4 |
| Pbfree Code | yes |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 16 |
| ECCN Code | EAR99 |
| Type | D-Type |
| Terminal Finish | Nickel/Palladium/Gold (Ni/Pd/Au) |
| Subcategory | FF/Latches |
| Packing Method | TR |
| Technology | CMOS |
| Voltage - Supply | 2V~5.5V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 2.5V |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| Base Part Number | 74LV174 |
| Function | Master Reset |
| Qualification Status | Not Qualified |
| Output Type | Non-Inverted |
| Number of Elements | 1 |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 5.5V |
| Power Supplies | 3.3V |
| Supply Voltage-Min (Vsup) | 2V |
| Number of Circuits | 7 |
| Load Capacitance | 50pF |
| Output Current | 12mA |
| Clock Frequency | 180MHz |
| Propagation Delay | 9.2 ns |
| Quiescent Current | 20μA |
| Turn On Delay Time | 3 ns |
| Family | LV/LV-A/LVX/H |
| Logic Function | D-Type, Flip-Flop |
| Current - Output High, Low | 12mA 12mA |
| Number of Bits per Element | 6 |
| Max Propagation Delay @ V, Max CL | 9.2ns @ 5V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 1.7pF |
| Number of Input Lines | 2 |
| Clock Edge Trigger Type | Positive Edge |
| Max Frequency@Nom-Sup | 50000000Hz |
| Height | 2mm |
| Length | 10.3mm |
| Width | 5.3mm |
| Thickness | 1.95mm |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
SN74LV174ANSR Overview
The flip flop is packaged in a case of 16-SOIC (0.209, 5.30mm Width). It is included in the package Tape & Reel (TR). Non-Invertedis the output configured for it. JK flip flop uses Positive Edgeas the trigger. Surface Mountis in the way of this electric part. It operates with a supply voltage of 2V~5.5V. It is at -40°C~85°C TAdegrees Celsius that the system is operating. A flip flop of this type is classified as a D-Type. JK flip flop is a part of the 74LVseries of FPGAs. It should not exceed 180MHzin its output frequency. In total, there are 1 elements. Currently, there are 16 terminations. The 74LV174 family contains this object. A voltage of 2.5V provides power to the D latch. The input capacitance of this JK flip flopis 1.7pF farads. Electronic devices of this type belong to the LV/LV-A/LVX/Hfamily. Electronic part Surface Mountis mounted in the way. This board has 16 pins. Edge triggering is a type of triggering that allows a circuit to become active at the positive edge or the negative edge of the clock signal. The clock edge trigger type of this device is Positive Edge. It is part of the FF/Latchesbase part number family. It reaches the maximum supply voltage (Vsup) at 5.5V. If you want to maintain normal operation, you should keep the supply voltage (Vsup) above 2V. Despite its superior flexibility, it relies on 7 circuits to achieve it. Compared to other similar T flip flops, this device offers reliable performance and is well suited for TR. The D latch operates on 3.3V volts. Featuring the maximum design flexibility, it has an output current of 12mA . 2input lines are available for you to choose from. Despite external influences, it consumes 20μAof quiescent current.
SN74LV174ANSR Features
Tape & Reel (TR) package
74LV series
16 pins
3.3V power supplies
SN74LV174ANSR Applications
There are a lot of Texas Instruments SN74LV174ANSR Flip Flops applications.
- 2 – Bit synchronous counter
- QML qualified product
- Asynchronous counter
- Common Clocks
- Buffered Clock
- Storage Registers
- Computing
- EMI reduction circuitry
- Divide a clock signal by 2 or 4
- Circuit Design
