XC6SLX9-2TQG144C
The XC6SLX9-2TQG144C offers a new, more efficient dual-register 6-input look-up table (LUT) logic and rich built-in system-level block selection, including second-generation 18 Kb (2 x 9 Kb) block RAM.
DSP48A1 slice, SDRAM memory controller, enhanced mixed-mode clock management block, Select™ technology, power-optimized high-speed serial transceiver block, advanced system-level power management modes, auto-detection of configuration options, and enhanced protection via AES and device DNA IP security.
The XC6SLX9-2TQG144C device provides a low-cost programmable alternative to custom ASIC products with unprecedented ease-of-use for high-volume logic designs, consumer-facing DSP designs, and cost-sensitive embedded application.
Main Features
• 45nm process optimized for cost and low power consumption
• Zero power sleep power down mode
• Pause mode maintains state and configuration
• Multi-pin wake-up for enhanced control
• Low power 1.0V core voltage (LX FPGA only, -1L)
• High performance 1.2V core voltage (LX and LXTFPGA, -2, -3 and -3N speed grades)
• Multi-Voltage, Multi-Standard Choice™ Interface Bank
• Data rates up to 1080 Mb/s per differential input/output
• Optional output drive up to 24 mA per pin
• 3.3V to 1.2V input/output standards and protocols
• Low cost HSTL and SSTL memory interface
• Hot-plug compliance
• Adjustable input/output slew rate for improved signal integrity
• High-speed GTP serial transceivers in LXT FPGAs
• Up to 3.2 Gb/s
• High-speed interfaces include: Serial ATA, Aurora, 1G Ethernet, PCI Express, OBSAI, CPRI, EPON, GPON, DisplayPort and XAUI
• Integrated Endpoint Block (LXT) for PCI Express designs
• Low-cost PCI® technology support, with 33 MHz, 32-bit and 64-bit specifications.
• Efficient DSP48A1 slice
• High performance algorithms and signal processing
• Pre-adder for auxiliary filter applications
• Integrated memory controller block
• DDR, DDR2, DDR3 and LPDDR support
• Data rates up to 800 Mb/s (12.8 Gb/s peak bandwidth)
• Multiport bus structure with independent FIFOs to reduce
• LUTs with dual flip-flops for pipeline-centric applications
• Block RAM with wide granularity
• Fast block RAM with byte write enable
• 18 Kb blocks, optionally programmable as two independent 9 Kb blocks of RAM
• Clock Management Tile (CMT) for enhanced performance
• Low noise, flexible clock
• Digital Clock Manager (DCM) eliminates clock skew and duty cycle distortion
The XC6SLX9-2TQG144C connects to the available logic resources of the input/output interface, and all inputs and outputs can be configured to be combined or registered. All inputs and outputs support Double Data Rate (DDR). Any input or output can be individually delayed by up to 256 increments (except -1L speed grade). This is implemented as IODELAY2. The same delay value can be used for data input or output. For bidirectional data lines, the propagation delay from input to output is automatic.
Finally, if you need to purchase the XC6SLX9-2TQG144C device, or want to know more about the parameters of this device, you can contact us.
