Parameters |
Surface Mount |
YES |
JESD-609 Code |
e3 |
Moisture Sensitivity Level (MSL) |
2 |
Number of Terminations |
28 |
Terminal Finish |
Matte Tin (Sn) |
Additional Feature |
WITH ADDITIONAL COMMON CLOCK; SET AND RESET INPUTS |
HTS Code |
8542.39.00.01 |
Subcategory |
FF/Latches |
Technology |
ECL |
Terminal Position |
QUAD |
Terminal Form |
J BEND |
Peak Reflow Temperature (Cel) |
235 |
Number of Functions |
3 |
Terminal Pitch |
1.27mm |
Time@Peak Reflow Temperature-Max (s) |
NOT SPECIFIED |
Pin Count |
28 |
JESD-30 Code |
S-PQCC-J28 |
Qualification Status |
Not Qualified |
Operating Temperature (Max) |
85°C |
Power Supplies |
-4.5V |
Temperature Grade |
OTHER |
Number of Bits |
1 |
Family |
100K |
Output Characteristics |
OPEN-EMITTER |
Output Polarity |
COMPLEMENTARY |
Logic IC Type |
D FLIP-FLOP |
Prop. Delay@Nom-Sup |
1.8 ns |
Trigger Type |
POSITIVE EDGE |
Propagation Delay (tpd) |
1.8 ns |
Power Supply Current-Max (ICC) |
122mA |
fmax-Min |
400 MHz |
Max Frequency@Nom-Sup |
400000000Hz |
Height Seated (Max) |
4.57mm |
Length |
11.43mm |
Width |
11.43mm |
RoHS Status |
Non-RoHS Compliant |
100331 Overview
It is configured with a trigger that uses a value of POSITIVE EDGE. A total of 28terminations have been recorded. It belongs to the family of electronic devices known as 100K. The part is included in FF/Latches. This flip flop is designed with 1 Bits. In order for the device to operate, it requires -4.5V power supplies. In addition, WITH ADDITIONAL COMMON CLOCK; SET AND RESET INPUTSis a characteristic of it. It uses D FLIP-FLOPas its logic IC. As a result, it is equipped with 3 functions . The D latch is equipped with 28 pins.
100331 Features
1 Bits
-4.5V power supplies
3 Functions
28 pin count
100331 Applications
There are a lot of Fairchild (ON Semiconductor) 100331 Flip Flops applications.
- Latch
- Bounce elimination switch
- Convert a momentary switch to a toggle switch
- Communications
- Frequency division
- Power down protection
- Bus hold
- Balanced 24 mA output drivers
- Individual Asynchronous Resets
- Frequency Divider circuits