Parameters |
Mount |
Surface Mount |
Package / Case |
CLCC |
Number of Pins |
84 |
Published |
2003 |
JESD-609 Code |
e0 |
Moisture Sensitivity Level (MSL) |
3 |
Number of Terminations |
84 |
ECCN Code |
3A001.A.2.C |
Terminal Finish |
Tin/Lead (Sn/Pb) |
Max Operating Temperature |
125°C |
Min Operating Temperature |
-55°C |
Additional Feature |
YES |
Subcategory |
Programmable Logic Devices |
Technology |
CMOS |
Terminal Position |
QUAD |
Terminal Form |
J BEND |
Peak Reflow Temperature (Cel) |
225 |
Supply Voltage |
3.3V |
Terminal Pitch |
1.27mm |
Frequency |
83MHz |
Time@Peak Reflow Temperature-Max (s) |
30 |
Pin Count |
84 |
Qualification Status |
Qualified |
Operating Supply Voltage |
3.3V |
Temperature Grade |
MILITARY |
Max Supply Voltage |
3.6V |
Min Supply Voltage |
3V |
Number of I/O |
69 |
Memory Type |
EEPROM |
Propagation Delay |
15 ns |
Turn On Delay Time |
15 ns |
Frequency (Max) |
83MHz |
Organization |
1 DEDICATED INPUTS, 69 I/O |
Programmable Logic Type |
EE PLD |
Number of Logic Blocks (LABs) |
8 |
Output Function |
MACROCELL |
Number of Macro Cells |
128 |
JTAG BST |
YES |
Number of Dedicated Inputs |
1 |
In-System Programmable |
YES |
Length |
29.21mm |
Width |
29.21mm |
Radiation Hardening |
No |
RoHS Status |
RoHS Compliant |
5962-9952201QYA Overview
The mobile phone network has 128 macro cells, which are cells that provide radio coverage from high-power cell sites (towers, antennas, or masts).The product is contained in a CLCC package.The device is programmed with 69 I/O ports.It is programmed that device terminations will be 84 .QUADis the terminal position of this electrical part.A voltage of 3.3V is used as the power supply for this device.It is a part of family [0].In this chip, the 84pins are programmed.The device can also be used to find [0].For high efficiency, the supply voltage should be maintained at [0].For storing data, it is recommended to use [0].Surface Mountmounts this electronic component.The pins are [0].It operates at a maximum supply voltage of 3.6V volts.Initially, it requires a voltage of 3Vas the minimum supply voltage.You can achieve 83MHzfrequencies.It is recommended that the operating temperature be greater than -55°C.It is recommended that the operating temperature be lower than 125°C.Its basic building block is composed of 8 logic blocks (LABs).The input signals are detected by 1dedicated inputs.It should be below 83MHzat the maximal frequency.This kind of FPGA is composed of EE PLD.
5962-9952201QYA Features
CLCC package
69 I/Os
84 pin count
84 pins
8 logic blocks (LABs)
5962-9952201QYA Applications
There are a lot of Cypress Semiconductor 5962-9952201QYA CPLDs applications.
- I2C BUS INTERFACE
- Wide Vin Industrial low power SMPS
- Page register
- Preset swapping
- INTERRUPT SYSTEM
- State machine control
- DDC INTERFACE
- Power automation
- Synchronous or asynchronous mode
- PULSE WIDTH MODULATION (PWM)