Parameters |
Factory Lead Time |
1 Week |
Package / Case |
896-BBGA, FCBGA |
Surface Mount |
YES |
Operating Temperature |
0°C~85°C TJ |
Packaging |
Tray |
Series |
Arria V SX |
JESD-609 Code |
e1 |
Part Status |
Active |
Moisture Sensitivity Level (MSL) |
3 (168 Hours) |
Number of Terminations |
896 |
Terminal Finish |
TIN SILVER COPPER |
Terminal Position |
BOTTOM |
Terminal Form |
BALL |
Peak Reflow Temperature (Cel) |
NOT SPECIFIED |
Supply Voltage |
1.1V |
Terminal Pitch |
1mm |
Time@Peak Reflow Temperature-Max (s) |
NOT SPECIFIED |
Base Part Number |
5ASXMB5 |
JESD-30 Code |
S-PBGA-B896 |
Supply Voltage-Max (Vsup) |
1.13V |
Supply Voltage-Min (Vsup) |
1.07V |
Number of I/O |
MCU - 208, FPGA - 250 |
Speed |
800MHz |
RAM Size |
64KB |
Core Processor |
Dual ARM® Cortex®-A9 MPCore™ with CoreSight™ |
Peripherals |
DMA, POR, WDT |
Clock Frequency |
622MHz |
Connectivity |
EBI/EMI, Ethernet, I2C, MMC/SD/SDIO, SPI, UART/USART, USB OTG |
Architecture |
MCU, FPGA |
Programmable Logic Type |
FIELD PROGRAMMABLE GATE ARRAY |
Primary Attributes |
FPGA - 462K Logic Elements |
Height Seated (Max) |
2.7mm |
Length |
31mm |
Width |
31mm |
RoHS Status |
RoHS Compliant |
This SoC is built on Dual ARM? Cortex?-A9 MPCore? with CoreSight? core processor(s).
This SoC is built on Dual ARM? Cortex?-A9 MPCore? with CoreSight? core processor(s).Assigned with the package 896-BBGA, FCBGA, this system on a chip comes from the manufacturer.With 64KB RAM implemented, this SoC chip provides users with a high level of performance.Using the MCU, FPGA technique, this SoC design's internal architecture is simple.Arria V SX is the series number of this system on chip SoC.This SoC meaning should have an average operating temperature of 0°C~85°C TJ when it is operating normally.This SoC security combines FPGA - 462K Logic Elements, an important feature to keep in mind.An advanced Tray package houses this SoC system on a chip.This SoC part has a total of MCU - 208, FPGA - 250 I/Os.Ideally, a power supply with a voltage of 1.1V should be used.The SoCs wireless cannot operate at a voltage greater than 1.13V because it is considered unsafe for the application.In order to run it, it must be fed by at least 1.07V of power.FIELD PROGRAMMABLE GATE ARRAY can be re-configured to serve different design needs.In total, there are 896 terminations, which makes system on a chip possible.Searching 5ASXMB5 will yield system on chips with similar specs and purposes.This SoC follows a 622MHz clock frequency.
Dual ARM? Cortex?-A9 MPCore? with CoreSight? processor.
64KB RAM.
Built on MCU, FPGA.
Clock Frequency: 622MHz
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