Parameters |
Mount |
Surface Mount |
Package / Case |
TFBGA |
Number of Pins |
100 |
JESD-609 Code |
e0 |
Pbfree Code |
no |
Number of Terminations |
100 |
Terminal Finish |
TIN LEAD |
Max Operating Temperature |
85°C |
Min Operating Temperature |
0°C |
Additional Feature |
YES |
HTS Code |
8542.39.00.01 |
Subcategory |
Programmable Logic Devices |
Technology |
CMOS |
Terminal Position |
BOTTOM |
Terminal Form |
BALL |
Peak Reflow Temperature (Cel) |
235 |
Supply Voltage |
1.8V |
Terminal Pitch |
0.5mm |
Time@Peak Reflow Temperature-Max (s) |
30 |
Pin Count |
100 |
Qualification Status |
Not Qualified |
Supply Voltage-Max (Vsup) |
1.89V |
Power Supplies |
1.2/3.31.8V |
Temperature Grade |
OTHER |
Supply Voltage-Min (Vsup) |
1.71V |
Number of I/O |
79 |
Clock Frequency |
118.3MHz |
Propagation Delay |
14 ns |
Programmable Logic Type |
FLASH PLD |
Number of Logic Blocks (LABs) |
160 |
Output Function |
MACROCELL |
Number of Macro Cells |
128 |
JTAG BST |
YES |
In-System Programmable |
YES |
Height Seated (Max) |
1.2mm |
Length |
6mm |
Width |
6mm |
RoHS Status |
RoHS Compliant |
5M160ZM100C5 Overview
Currently, there are 128 macro cells, which are low-power cell sites (towers, antennas, masts) that serve as radio coverage.The item is packaged with TFBGA.The device is programmed with 79 I/O ports.There are 100 terminations, which are the practice of ending a transmission line with a device that matches the characteristic impedance of the line.This electrical part is wired with a terminal position of BOTTOM.A voltage of 1.8V is used as the power supply for this device.This part is part of the family [0].The chip is programmed with 100 pins.Additionally, this device is capable of displaying [0].In this case, Surface Mountis used to mount the electronic component.The device has a pinout of [0].Currently, it is powered by 1.2/3.31.8Vsources.In this case, the maximum supply voltage (Vsup) is 1.89V.Operating temperatures should be higher than 0°C.It is recommended that the operating temperature be below 85°C.Its basic building block is composed of 160 logic blocks (LABs).There should be a higher supply voltage (Vsup) than 1.71V.Its clock frequency should not exceed 118.3MHz.There are several types of programmable logic that can be categorized as FLASH PLD.
5M160ZM100C5 Features
TFBGA package
79 I/Os
100 pin count
100 pins
1.2/3.31.8V power supplies
160 logic blocks (LABs)
5M160ZM100C5 Applications
There are a lot of Altera 5M160ZM100C5 CPLDs applications.
- STANDARD SERIAL INTERFACE UART
- Power Meter SMPS
- Synchronous or asynchronous mode
- I2C BUS INTERFACE
- Portable digital devices
- Programmable power management
- Digital multiplexers
- Digital systems
- PULSE WIDTH MODULATION (PWM)
- Battery operated portable devices