Parameters |
Mount |
Surface Mount |
Package / Case |
TFBGA |
Number of Pins |
68 |
JESD-609 Code |
e0 |
Pbfree Code |
no |
Number of Terminations |
68 |
Terminal Finish |
TIN LEAD |
Max Operating Temperature |
100°C |
Min Operating Temperature |
-40°C |
Additional Feature |
YES |
HTS Code |
8542.39.00.01 |
Subcategory |
Programmable Logic Devices |
Technology |
CMOS |
Terminal Position |
BOTTOM |
Terminal Form |
BALL |
Peak Reflow Temperature (Cel) |
NOT SPECIFIED |
Supply Voltage |
1.8V |
Terminal Pitch |
0.5mm |
Time@Peak Reflow Temperature-Max (s) |
NOT SPECIFIED |
Pin Count |
68 |
Qualification Status |
Not Qualified |
Supply Voltage-Max (Vsup) |
1.89V |
Power Supplies |
1.2/3.31.8V |
Temperature Grade |
INDUSTRIAL |
Supply Voltage-Min (Vsup) |
1.71V |
Number of I/O |
52 |
Clock Frequency |
118.3MHz |
Propagation Delay |
14 ns |
Programmable Logic Type |
FLASH PLD |
Number of Logic Blocks (LABs) |
160 |
Output Function |
MACROCELL |
Number of Macro Cells |
128 |
JTAG BST |
YES |
In-System Programmable |
YES |
Height Seated (Max) |
1.2mm |
Length |
5mm |
Width |
5mm |
RoHS Status |
RoHS Compliant |
5M160ZM68I5 Overview
There are 128 macro cells. A macro cell is a cell in a mobile phone network that provides radio coverage through the use of a high-power cell site (tower, antenna or mast).TFBGAis the package in which it resides.This device has 52 I/O ports programmed into it.The termination of a device is set to [0].As the terminal position of this electrical part is [0], it serves as an important access point for passengers or freight.Power is provided by a supply voltage of 1.8V volts.The part belongs to Programmable Logic Devices family.It is programmed with 68 pins.When using this device, YEScan also be found.A Surface Mountis mounted on this electronic component.The 68pins are designed into the board.In order for the device to operate, it requires 1.2/3.31.8V power supplies.In this case, the maximum supply voltage (Vsup) is 1.89V.It is recommended that the operating temperature exceed -40°C.A temperature below 100°Cshould be used as the operating temperature.There are 160logic blocks (LABs) that make up its basic building block.A supply voltage (Vsup) of greater than 1.71V should be used.This device should not have an clock frequency greater than 118.3MHz.A programmable logic type is classified as FLASH PLD.
5M160ZM68I5 Features
TFBGA package
52 I/Os
68 pin count
68 pins
1.2/3.31.8V power supplies
160 logic blocks (LABs)
5M160ZM68I5 Applications
There are a lot of Altera 5M160ZM68I5 CPLDs applications.
- SFP, QSFP, QSFP-DD, OSFP, Mini-SAS HD Port Management
- ToR/Aggregation/Core Switch and Router
- Digital multiplexers
- ON-CHIP OSCILLATOR CIRCUIT
- Digital designs
- Interface bridging
- Configurable Addressing of I/O Boards
- Software-Driven Hardware Configuration
- Parity generators
- Power up sequencing