Parameters |
Mount |
Surface Mount |
Package / Case |
TFBGA |
Number of Pins |
100 |
JESD-609 Code |
e0 |
Pbfree Code |
no |
Number of Terminations |
100 |
Terminal Finish |
TIN LEAD |
Max Operating Temperature |
85°C |
Min Operating Temperature |
0°C |
Additional Feature |
YES |
HTS Code |
8542.39.00.01 |
Subcategory |
Programmable Logic Devices |
Technology |
CMOS |
Terminal Position |
BOTTOM |
Terminal Form |
BALL |
Peak Reflow Temperature (Cel) |
235 |
Supply Voltage |
1.8V |
Terminal Pitch |
0.5mm |
Time@Peak Reflow Temperature-Max (s) |
30 |
Pin Count |
100 |
Qualification Status |
Not Qualified |
Supply Voltage-Max (Vsup) |
1.89V |
Power Supplies |
1.81.2/3.3V |
Temperature Grade |
OTHER |
Supply Voltage-Min (Vsup) |
1.71V |
Number of I/O |
79 |
Clock Frequency |
118.3MHz |
Propagation Delay |
14 ns |
Programmable Logic Type |
FLASH PLD |
Number of Logic Blocks (LABs) |
240 |
Output Function |
MACROCELL |
Number of Macro Cells |
192 |
JTAG BST |
YES |
In-System Programmable |
YES |
Height Seated (Max) |
1.2mm |
Length |
6mm |
Width |
6mm |
RoHS Status |
RoHS Compliant |
5M240ZM100C5 Overview
This network has 192macro cells, which are cells that provide radio coverage provided by a high-power cell site (tower, antenna, mast).A TFBGA package contains the item.This device has 79 I/O ports programmed into it.100terminations are programmed into the device.This electrical part is wired with a terminal position of BOTTOM.A voltage of 1.8Vprovides power to the device.This part is included in Programmable Logic Devices.It has 100pins programmed.When using this device, YESis also available.This device is mounted by Surface Mount.There are 100 pins on the device.A power supply of 1.81.2/3.3Vvolts is required to operate this device.Supply voltage (Vsup) reaches a maximum of 1.89V.It is recommended that the operating temperature be higher than 0°C.Temperatures should be lower than 85°C when operating.The program consists of 240 logic blocks (LABs).It should be possible for Vsup to exceed 1.71Vat the supply voltage.This device should not have an clock frequency greater than 118.3MHz.Programmable logic types can be divided into FLASH PLD.
5M240ZM100C5 Features
TFBGA package
79 I/Os
100 pin count
100 pins
1.81.2/3.3V power supplies
240 logic blocks (LABs)
5M240ZM100C5 Applications
There are a lot of Altera 5M240ZM100C5 CPLDs applications.
- Bootloaders for FPGAs
- Field programmable gate
- State machine control
- Network Interface Card (NIC) and Host Bus Adapter (HBA)
- Pattern recognition
- High speed graphics processing
- ROM patching
- Auxiliary Power Supply Isolated and Non-isolated
- Portable digital devices
- LED Lighting systems