Parameters |
Mount |
Surface Mount |
Package / Case |
TFBGA |
Number of Pins |
100 |
JESD-609 Code |
e0 |
Pbfree Code |
no |
Number of Terminations |
100 |
Terminal Finish |
TIN LEAD |
Max Operating Temperature |
85°C |
Min Operating Temperature |
0°C |
Additional Feature |
YES |
HTS Code |
8542.39.00.01 |
Subcategory |
Programmable Logic Devices |
Technology |
CMOS |
Terminal Position |
BOTTOM |
Terminal Form |
BALL |
Peak Reflow Temperature (Cel) |
NOT SPECIFIED |
Supply Voltage |
1.8V |
Terminal Pitch |
0.5mm |
Time@Peak Reflow Temperature-Max (s) |
NOT SPECIFIED |
Pin Count |
100 |
Qualification Status |
Not Qualified |
Supply Voltage-Max (Vsup) |
1.89V |
Power Supplies |
1.81.2/3.3V |
Temperature Grade |
OTHER |
Supply Voltage-Min (Vsup) |
1.71V |
Number of I/O |
74 |
Clock Frequency |
184.1MHz |
Propagation Delay |
9.5 ns |
Programmable Logic Type |
FLASH PLD |
Number of Logic Blocks (LABs) |
570 |
Output Function |
MACROCELL |
Number of Macro Cells |
440 |
JTAG BST |
YES |
In-System Programmable |
YES |
Height Seated (Max) |
1.2mm |
Length |
6mm |
Width |
6mm |
RoHS Status |
RoHS Compliant |
5M570ZM100C4 Overview
The mobile phone network has 440 macro cells, which are cells that provide radio coverage from high-power cell sites (towers, antennas, or masts).It is embedded in the TFBGA package.There are 74 I/Os on the board.It is programmed to terminate devices at [0].As the terminal position of this electrical part is [0], it serves as an important access point for passengers or freight.Power is supplied by a voltage of 1.8V volts.It is a part of the family [0].A chip with 100pins is programmed.If this device is used, you will also be able to find [0].This electronic part is mounted in the way of Surface Mount.It is designed with 100 pins.This device runs on 1.81.2/3.3Vvolts of electricity.In this case, the maximum supply voltage (Vsup) reaches 1.89V.Operating temperatures should be higher than 0°C.Temperatures should be lower than 85°C when operating.It consists of 570 logic blocks (LABs).A supply voltage (Vsup) of greater than 1.71V should be used.It should not exceed 184.1MHzin its clock frequency.This kind of FPGA is composed of FLASH PLD.
5M570ZM100C4 Features
TFBGA package
74 I/Os
100 pin count
100 pins
1.81.2/3.3V power supplies
570 logic blocks (LABs)
5M570ZM100C4 Applications
There are a lot of Altera 5M570ZM100C4 CPLDs applications.
- I/O expansion
- Software Configuration of Add-In Boards
- Wireless Infrastructure Base Band Unit and Remote Radio Unit
- Portable digital devices
- Digital multiplexers
- LED Lighting systems
- DMA control
- ANALOG-TO-DIGITAL CONVERTOR (ADC)
- State machine design
- ToR/Aggregation/Core Switch and Router