Parameters |
Mounting Type |
Surface Mount |
Package / Case |
48-TFSOP (0.240, 6.10mm Width) |
Surface Mount |
YES |
Operating Temperature |
-40°C~85°C TA |
Packaging |
Tube |
Series |
74ABT |
Part Status |
Obsolete |
Moisture Sensitivity Level (MSL) |
1 (Unlimited) |
Number of Terminations |
48 |
Type |
D-Type |
Subcategory |
FF/Latches |
Voltage - Supply |
4.5V~5.5V |
Terminal Position |
DUAL |
Terminal Form |
GULL WING |
Supply Voltage |
5V |
Terminal Pitch |
0.5mm |
Base Part Number |
74ABT16273 |
Function |
Master Reset |
Qualification Status |
Not Qualified |
Output Type |
Non-Inverted |
Number of Elements |
2 |
Power Supplies |
5V |
Clock Frequency |
240MHz |
Current - Quiescent (Iq) |
1mA |
Current - Output High, Low |
32mA 64mA |
Max I(ol) |
0.064 A |
Number of Bits per Element |
8 |
Max Propagation Delay @ V, Max CL |
3.4ns @ 5V, 50pF |
Prop. Delay@Nom-Sup |
4 ns |
Trigger Type |
Positive Edge |
Input Capacitance |
4pF |
Max Frequency@Nom-Sup |
150000000Hz |
RoHS Status |
ROHS3 Compliant |
74ABT16273DGG,512 Overview
It is embeded in 48-TFSOP (0.240, 6.10mm Width) case. The Tubepackage contains it. In the configuration, Non-Invertedis used as the output. It is configured with the trigger Positive Edge. The electronic part is mounted in the way of Surface Mount. A voltage of 4.5V~5.5Vis used as the supply voltage. In this case, the operating temperature is -40°C~85°C TA. A flip flop of this type is classified as a D-Type. JK flip flop is a part of the 74ABTseries of FPGAs. You should not exceed 240MHzin its output frequency. A total of 2 elements are present. It consumes 1mA of quiescent A total of 48 terminations have been made. The object belongs to the 74ABT16273 family. An input voltage of 5Vpowers the D latch. This JK flip flop has a 4pFfarad input capacitance. This part is included in FF/Latches. It runs on 5Vvolts of power.
74ABT16273DGG,512 Features
Tube package
74ABT series
5V power supplies
74ABT16273DGG,512 Applications
There are a lot of NXP USA Inc. 74ABT16273DGG,512 Flip Flops applications.
- EMI reduction circuitry
- Divide a clock signal by 2 or 4
- Balanced Propagation Delays
- Individual Asynchronous Resets
- Asynchronous counter
- Latch-up performance
- Parallel data storage
- Counters
- Single Up Count-Control Line
- Memory