74AC11175N
| Parameters | |
|---|---|
| Mount | Through Hole |
| Mounting Type | Through Hole |
| Package / Case | 20-DIP (0.300, 7.62mm) |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tube |
| Series | 74AC |
| Pbfree Code | no |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 20 |
| Type | D-Type |
| Subcategory | FF/Latches |
| Technology | CMOS |
| Voltage - Supply | 3V~5.5V |
| Terminal Position | DUAL |
| Peak Reflow Temperature (Cel) | NOT SPECIFIED |
| Supply Voltage | 5V |
| Reach Compliance Code | not_compliant |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| Base Part Number | 74AC11175 |
| JESD-30 Code | R-PDIP-T20 |
| Function | Master Reset |
| Qualification Status | Not Qualified |
| Output Type | Differential |
| Number of Elements | 1 |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 5.5V |
| Power Supplies | 3.3/5V |
| Supply Voltage-Min (Vsup) | 3V |
| Number of Circuits | 4 |
| Load Capacitance | 50pF |
| Number of Bits | 4 |
| Clock Frequency | 150MHz |
| Turn On Delay Time | 4.5 ns |
| Family | AC |
| Current - Quiescent (Iq) | 8μA |
| Current - Output High, Low | 24mA 24mA |
| Max Propagation Delay @ V, Max CL | 8.5ns @ 5V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 4pF |
| Propagation Delay (tpd) | 9.3 ns |
| Clock Edge Trigger Type | Positive Edge |
| Height Seated (Max) | 5.08mm |
| Width | 7.62mm |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Contains Lead |
74AC11175N Overview
As a result, it is packaged as 20-DIP (0.300, 7.62mm). The package Tubecontains it. In the configuration, Differentialis used as the output. It is configured with a trigger that uses Positive Edge. Through Holemounts this electrical part. It operates with a supply voltage of 3V~5.5V. The operating temperature is -40°C~85°C TA. Logic flip flops of this type are classified as D-Type. In FPGA terms, D flip flop is a type of 74ACseries FPGA. In order for it to function properly, its output frequency should not exceed 150MHz. D latch consists of 1 elements. As a result, it consumes 8μA quiescent current. In 20terminations, a transmission line is terminated with a JK flip flop that matches its characteristic impedance. JK flip flop belongs to 74AC11175 family. It is powered by a voltage of 5V . A 4pFfarad input capacitance is provided by this T flip flop. The electronic device belongs to the ACfamily. There is an electronic part that is mounted in the way of Through Hole. There is a clock edge trigger type of Positive Edgeon this device. There is a base part number FF/Latchesfor the RS flip flops. This flip flop is designed with 4 Bits. The maximal supply voltage (Vsup) reaches 5.5V. A normal operating voltage (Vsup) should remain above 3V. Due to its superior flexibility, it uses 4 circuits. In order for the device to operate, it requires 3.3/5V power supplies.
74AC11175N Features
Tube package
74AC series
4 Bits
3.3/5V power supplies
74AC11175N Applications
There are a lot of Texas Instruments 74AC11175N Flip Flops applications.
- Shift Registers
- Parallel data storage
- Storage Registers
- Digital electronics systems
- 2 – Bit synchronous counter
- Frequency division
- Balanced 24 mA output drivers
- Functionally equivalent to the MC10/100EL29
- Dynamic threshold performance
- QML qualified product
