Parameters |
Mounting Type |
Surface Mount |
Package / Case |
20-SOIC (0.295, 7.50mm Width) |
Surface Mount |
YES |
Operating Temperature |
-40°C~85°C TA |
Packaging |
Tape & Reel (TR) |
Series |
74AC |
JESD-609 Code |
e3 |
Pbfree Code |
yes |
Part Status |
Obsolete |
Moisture Sensitivity Level (MSL) |
1 (Unlimited) |
Number of Terminations |
20 |
Type |
D-Type |
Terminal Finish |
MATTE TIN |
Additional Feature |
WITH HOLD MODE |
Technology |
CMOS |
Voltage - Supply |
2V~6V |
Terminal Position |
DUAL |
Terminal Form |
GULL WING |
Peak Reflow Temperature (Cel) |
260 |
Supply Voltage |
3.3V |
Reach Compliance Code |
unknown |
Time@Peak Reflow Temperature-Max (s) |
NOT SPECIFIED |
JESD-30 Code |
R-PDSO-G20 |
Function |
Standard |
Qualification Status |
COMMERCIAL |
Output Type |
Non-Inverted |
Number of Elements |
1 |
Supply Voltage-Max (Vsup) |
6V |
Supply Voltage-Min (Vsup) |
2V |
Clock Frequency |
175MHz |
Family |
AC |
Current - Quiescent (Iq) |
40μA |
Current - Output High, Low |
24mA 24mA |
Output Polarity |
TRUE |
Number of Bits per Element |
8 |
Max Propagation Delay @ V, Max CL |
9ns @ 5V, 50pF |
Trigger Type |
Positive Edge |
Input Capacitance |
4.5pF |
Height Seated (Max) |
2.642mm |
Width |
7.5mm |
RoHS Status |
ROHS3 Compliant |
74AC377SCX Overview
20-SOIC (0.295, 7.50mm Width)is the way it is packaged. You can find it in the Tape & Reel (TR)package. This output is configured with Non-Inverted. The trigger it is configured with uses Positive Edge. Surface Mountis positioned in the way of this electronic part. The JK flip flop operates at a voltage of 2V~6V. -40°C~85°C TAis the operating temperature. D-Typeis the type of this D latch. FPGAs belonging to the 74ACseries contain this type of chip. There should be no greater frequency than 175MHzon its output. In total, it contains 1 elements. T flip flop consumes 40μA quiescent energy. 20terminations have occurred. The power supply voltage is 3.3V. Its input capacitance is 4.5pFfarads. Devices in the ACfamily are electronic devices. It reaches 6Vwhen the supply voltage is maximal (Vsup). Normally, the supply voltage (Vsup) should be above 2V. Additionally, you may refer to the D latch's additional WITH HOLD MODE.
74AC377SCX Features
Tape & Reel (TR) package
74AC series
74AC377SCX Applications
There are a lot of Rochester Electronics, LLC 74AC377SCX Flip Flops applications.
- Clock pulse
- Bus hold
- Matched Rise and Fall
- Modulo – n – counter
- Load Control
- Data storage
- Divide a clock signal by 2 or 4
- Supports Live Insertion
- Communications
- CMOS Process