74ACT109SC
| Parameters | |
|---|---|
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 16-SOIC (0.154, 3.90mm Width) |
| Number of Pins | 16 |
| Supplier Device Package | 16-SOIC |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tube |
| Series | 74ACT |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Type | JK Type |
| Max Operating Temperature | 85°C |
| Min Operating Temperature | -40°C |
| Voltage - Supply | 4.5V~5.5V |
| Frequency | 210MHz |
| Base Part Number | 74ACT109 |
| Function | Set(Preset) and Reset |
| Output Type | Differential |
| Operating Supply Voltage | 5V |
| Number of Elements | 2 |
| Polarity | Non-Inverting |
| Number of Circuits | 2 |
| Max Supply Voltage | 5.5V |
| Min Supply Voltage | 4.5V |
| Output Current | 24mA |
| Number of Bits | 2 |
| Clock Frequency | 210MHz |
| Propagation Delay | 11 ns |
| Turn On Delay Time | 7 ns |
| Logic Function | AND, Flip-Flop |
| Current - Quiescent (Iq) | 20μA |
| Current - Output High, Low | 24mA 24mA |
| Number of Bits per Element | 1 |
| Max Propagation Delay @ V, Max CL | 11ns @ 5V, 50pF |
| Trigger Type | Positive Edge |
| High Level Output Current | -24mA |
| Input Capacitance | 4.5pF |
| Low Level Output Current | 24mA |
| Number of Input Lines | 5 |
| Number of Output Lines | 2 |
| Clock Edge Trigger Type | Positive Edge |
| RoHS Status | RoHS Compliant |
| Lead Free | Lead Free |
74ACT109SC Overview
The flip flop is packaged in a case of 16-SOIC (0.154, 3.90mm Width). A package named Tubeincludes it. Differentialis the output configured for it. The trigger configured with it uses Positive Edge. It is mounted in the way of Surface Mount. The JK flip flop operates with an input voltage of 4.5V~5.5V volts. -40°C~85°C TAis the operating temperature. JK Typeis the type of this D latch. This type of FPGA is a part of the 74ACT series. A frequency of 210MHzshould be the maximum output frequency. The element count is 2 . As a result, it consumes 20μA quiescent current and is not affected by external forces. D latch belongs to the 74ACT109 family. JK flip flop input capacitance is 4.5pF farads. In this case, the electronic component is mounted in the way of Surface Mount. The 16pins are designed into the board. There is a clock edge trigger type of Positive Edgeon this device. This flip flop is designed with 2 Bits. The superior flexibility of this product is achieved by using 2 circuits. If high efficiency is desired, the supply voltage should be kept at 5V. With an output current of 24mA, it is possible to design the device in any way you want. There are 2 output lines in this JK flip flop. Currently, there are 5 input lines present. In this case, the high level output current is set to -24mA. There is 24mA output current at the low level. Ideally, the operating temperature should be lower than 85°C. Temperatures above -40°Cshould be used. The system operates with a minimum supply voltage of 4.5V. 5.5Vis the maximum supply voltage it supports. This frequency can be achieved at 210MHz.
74ACT109SC Features
Tube package
74ACT series
16 pins
2 Bits
74ACT109SC Applications
There are a lot of ON Semiconductor 74ACT109SC Flip Flops applications.
- Single Down Count-Control Line
- QML qualified product
- Divide a clock signal by 2 or 4
- ATE
- Reduced system switching noise
- ESD performance
- Supports Live Insertion
- Event Detectors
- Individual Asynchronous Resets
- Latch
