74ACT174SC
| Parameters | |
|---|---|
| Mounting Type | Surface Mount |
| Package / Case | 16-SOIC (0.154, 3.90mm Width) |
| Surface Mount | YES |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tube |
| Series | 74ACT |
| JESD-609 Code | e3 |
| Pbfree Code | yes |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 16 |
| Type | D-Type |
| Terminal Finish | MATTE TIN |
| Technology | CMOS |
| Voltage - Supply | 4.5V~5.5V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 5V |
| Reach Compliance Code | unknown |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| Function | Master Reset |
| Qualification Status | COMMERCIAL |
| Output Type | Non-Inverted |
| Number of Elements | 1 |
| Supply Voltage-Max (Vsup) | 5.5V |
| Supply Voltage-Min (Vsup) | 4.5V |
| Clock Frequency | 200MHz |
| Family | ACT |
| Current - Quiescent (Iq) | 40μA |
| Current - Output High, Low | 24mA 24mA |
| Output Polarity | TRUE |
| Number of Bits per Element | 6 |
| Max Propagation Delay @ V, Max CL | 10.5ns @ 5V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 4.5pF |
| Length | 9.9mm |
| Width | 3.9mm |
| RoHS Status | ROHS3 Compliant |
74ACT174SC Overview
It is packaged in the way of 16-SOIC (0.154, 3.90mm Width). It is included in the package Tube. T flip flop is configured with an output of Non-Inverted. It is configured with a trigger that uses Positive Edge. Surface Mountmounts this electrical part. A voltage of 4.5V~5.5Vis used as the supply voltage. In the operating environment, the temperature is -40°C~85°C TA. This electronic flip flop is of type D-Type. In this case, it is a type of FPGA belonging to the 74ACT series. Its output frequency should not exceed 200MHz. In total, there are 1 elements. It consumes 40μA of quiescent current without being affected by external factors. There are 16 terminations, which are the practice of ending a transmission line with a device that matches the characteristic impedance of the line. An input voltage of 5Vpowers the D latch. Input capacitance of this device is 4.5pF farads. In this case, the D flip flop belongs to the ACTfamily. As soon as Vsup reaches 5.5V, the maximum supply voltage is reached. For normal operation, the supply voltage (Vsup) should be kept above 4.5V.
74ACT174SC Features
Tube package
74ACT series
74ACT174SC Applications
There are a lot of Rochester Electronics, LLC 74ACT174SC Flip Flops applications.
- Single Down Count-Control Line
- Supports Live Insertion
- ATE
- Guaranteed simultaneous switching noise level
- Count Modes
- Computers
- Differential Individual
- Consumer
- Load Control
- CMOS Process
