74ACT374SCX
| Parameters | |
|---|---|
| Mounting Type | Surface Mount |
| Package / Case | 20-SOIC (0.295, 7.50mm Width) |
| Surface Mount | YES |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tape & Reel (TR) |
| Published | 1998 |
| Series | 74ACT |
| JESD-609 Code | e3 |
| Pbfree Code | yes |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 20 |
| Type | D-Type |
| Terminal Finish | Matte Tin (Sn) |
| Technology | CMOS |
| Voltage - Supply | 4.5V~5.5V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 5V |
| Reach Compliance Code | unknown |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| JESD-30 Code | R-PDSO-G20 |
| Function | Standard |
| Output Type | Tri-State, Non-Inverted |
| Number of Elements | 1 |
| Supply Voltage-Max (Vsup) | 5.5V |
| Supply Voltage-Min (Vsup) | 4.5V |
| Number of Ports | 2 |
| Clock Frequency | 160MHz |
| Family | ACT |
| Current - Quiescent (Iq) | 40μA |
| Output Characteristics | 3-STATE |
| Current - Output High, Low | 24mA 24mA |
| Output Polarity | TRUE |
| Number of Bits per Element | 8 |
| Max Propagation Delay @ V, Max CL | 10ns @ 5V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 4.5pF |
| Height Seated (Max) | 2.65mm |
| Width | 7.5mm |
| RoHS Status | ROHS3 Compliant |
74ACT374SCX Overview
It is packaged in the way of 20-SOIC (0.295, 7.50mm Width). As part of the package Tape & Reel (TR), it is embedded. In the configuration, Tri-State, Non-Invertedis used as the output. Positive Edgeis the trigger it is configured with. There is an electric part mounted in the way of Surface Mount. The JK flip flop operates at a voltage of 4.5V~5.5V. A temperature of -40°C~85°C TAis used in the operation. D-Typedescribes this flip flop. In FPGA terms, D flip flop is a type of 74ACTseries FPGA. It should not exceed 160MHzin its output frequency. The element count is 1 . It consumes 40μA of quiescent current without being affected by external factors. There are 20 terminations, which are the practice of ending a transmission line with a device that matches the characteristic impedance of the line. The D flip flop is powered by a voltage of 5V . Its input capacitance is 4.5pFfarads. Devices in the ACTfamily are electronic devices. As soon as Vsup reaches 5.5V, the maximum supply voltage is reached. Normal operation requires a supply voltage (Vsup) above 4.5V. The flip flop contains 2ports.
74ACT374SCX Features
Tape & Reel (TR) package
74ACT series
74ACT374SCX Applications
There are a lot of Rochester Electronics, LLC 74ACT374SCX Flip Flops applications.
- Frequency division
- Memory
- Set-reset capability
- Instrumentation
- Latch
- Communications
- Buffer registers
- Reduced system switching noise
- EMI reduction circuitry
- Patented noise
