74ACT374SJ
| Parameters | |
|---|---|
| Mounting Type | Surface Mount |
| Package / Case | 20-SOIC (0.209, 5.30mm Width) |
| Surface Mount | YES |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tube |
| Series | 74ACT |
| JESD-609 Code | e3 |
| Pbfree Code | yes |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 20 |
| Type | D-Type |
| Terminal Finish | MATTE TIN |
| Technology | CMOS |
| Voltage - Supply | 4.5V~5.5V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 5V |
| Reach Compliance Code | unknown |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| JESD-30 Code | R-PDSO-G20 |
| Function | Standard |
| Output Type | Tri-State, Non-Inverted |
| Number of Elements | 1 |
| Supply Voltage-Max (Vsup) | 5.5V |
| Supply Voltage-Min (Vsup) | 4.5V |
| Number of Ports | 2 |
| Clock Frequency | 160MHz |
| Family | ACT |
| Current - Quiescent (Iq) | 40μA |
| Output Characteristics | 3-STATE |
| Current - Output High, Low | 24mA 24mA |
| Output Polarity | TRUE |
| Number of Bits per Element | 8 |
| Max Propagation Delay @ V, Max CL | 10ns @ 5V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 4.5pF |
| Width | 5.3mm |
| RoHS Status | ROHS3 Compliant |
74ACT374SJ Overview
In the form of 20-SOIC (0.209, 5.30mm Width), it has been packaged. It is included in the package Tube. The output it is configured with uses Tri-State, Non-Inverted. In the configuration of the trigger, Positive Edgeis used. Surface Mountis occupied by this electronic component. Powered by a 4.5V~5.5Vvolt supply, it operates as follows. -40°C~85°C TAis the operating temperature. D-Typeis the type of this D latch. In terms of FPGAs, it belongs to the 74ACT series. A frequency of 160MHzshould be the maximum output frequency. In total, it contains 1 elements. Despite external influences, it consumes 40μAof quiescent current. A total of 20terminations have been recorded. It is powered by a voltage of 5V . Its input capacitance is 4.5pFfarads. A device of this type belongs to the family of ACT. As soon as 5.5Vis reached, Vsup reaches its maximum value. The supply voltage (Vsup) should be maintained above 4.5V for normal operation. The flip flop has 2ports embedded within it.
74ACT374SJ Features
Tube package
74ACT series
74ACT374SJ Applications
There are a lot of Rochester Electronics, LLC 74ACT374SJ Flip Flops applications.
- Balanced 24 mA output drivers
- Parallel data storage
- QML qualified product
- Frequency division
- Computers
- Pattern generators
- Differential Individual
- Computing
- Instrumentation
- Patented noise
