74ACT377SJX
| Parameters | |
|---|---|
| Mounting Type | Surface Mount |
| Package / Case | 20-SOIC (0.209, 5.30mm Width) |
| Surface Mount | YES |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74ACT |
| JESD-609 Code | e3 |
| Pbfree Code | yes |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 20 |
| Type | D-Type |
| Terminal Finish | MATTE TIN |
| Additional Feature | WITH HOLD MODE |
| Technology | CMOS |
| Voltage - Supply | 4.5V~5.5V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 5V |
| Reach Compliance Code | unknown |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| JESD-30 Code | R-PDSO-G20 |
| Function | Standard |
| Qualification Status | Not Qualified |
| Output Type | Non-Inverted |
| Number of Elements | 1 |
| Supply Voltage-Max (Vsup) | 5.5V |
| Supply Voltage-Min (Vsup) | 4.5V |
| Clock Frequency | 175MHz |
| Family | ACT |
| Current - Quiescent (Iq) | 40μA |
| Current - Output High, Low | 24mA 24mA |
| Output Polarity | TRUE |
| Number of Bits per Element | 8 |
| Max Propagation Delay @ V, Max CL | 10ns @ 5V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 4.5pF |
| Width | 5.3mm |
| RoHS Status | ROHS3 Compliant |
74ACT377SJX Overview
The flip flop is packaged in a case of 20-SOIC (0.209, 5.30mm Width). As part of the package Tape & Reel (TR), it is embedded. T flip flop uses Non-Invertedas its output configuration. In the configuration of the trigger, Positive Edgeis used. This electronic part is mounted in the way of Surface Mount. A voltage of 4.5V~5.5Vis used as the supply voltage. In the operating environment, the temperature is -40°C~85°C TA. This logic flip flop is classified as type D-Type. FPGAs belonging to the 74ACTseries contain this type of chip. Its output frequency should not exceed 175MHz. There are 1 elements in it. There is 40μA quiescent consumption. A total of 20terminations have been recorded. The D flip flop is powered by a voltage of 5V . This T flip flop has a capacitance of 4.5pF farads at the input. ACTis the family of this D flip flop. The maximal supply voltage (Vsup) reaches 5.5V. If you want to maintain normal operation, you should keep the supply voltage (Vsup) above 4.5V. In addition, you can refer to the additinal WITH HOLD MODE of the D latch.
74ACT377SJX Features
Tape & Reel (TR) package
74ACT series
74ACT377SJX Applications
There are a lot of Rochester Electronics, LLC 74ACT377SJX Flip Flops applications.
- ESCC
- CMOS Process
- Parallel data storage
- Power down protection
- Counters
- Automotive
- Bounce elimination switch
- Storage registers
- Frequency division
- Latch
