74ACTQ273SJX
| Parameters | |
|---|---|
| Mounting Type | Surface Mount |
| Package / Case | 20-SOIC (0.209, 5.30mm Width) |
| Surface Mount | YES |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74ACTQ |
| JESD-609 Code | e3 |
| Pbfree Code | yes |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 20 |
| Type | D-Type |
| Terminal Finish | MATTE TIN |
| Technology | CMOS |
| Voltage - Supply | 4.5V~5.5V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 5V |
| Reach Compliance Code | unknown |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| JESD-30 Code | R-PDSO-G20 |
| Function | Master Reset |
| Qualification Status | Not Qualified |
| Output Type | Non-Inverted |
| Number of Elements | 1 |
| Supply Voltage-Max (Vsup) | 5.5V |
| Supply Voltage-Min (Vsup) | 4.5V |
| Clock Frequency | 189MHz |
| Family | ACT |
| Current - Quiescent (Iq) | 40μA |
| Current - Output High, Low | 24mA 24mA |
| Output Polarity | TRUE |
| Number of Bits per Element | 8 |
| Max Propagation Delay @ V, Max CL | 8.5ns @ 5V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 4.5pF |
| Propagation Delay (tpd) | 9 ns |
| Width | 5.3mm |
| RoHS Status | ROHS3 Compliant |
74ACTQ273SJX Overview
It is embeded in 20-SOIC (0.209, 5.30mm Width) case. There is an embedded version in the package Tape & Reel (TR). In the configuration, Non-Invertedis used as the output. It is configured with a trigger that uses Positive Edge. Surface Mountis positioned in the way of this electronic part. The supply voltage is set to 4.5V~5.5V. A temperature of -40°C~85°C TAis considered to be the operating temperature. D-Typedescribes this flip flop. JK flip flop belongs to the 74ACTQseries of FPGAs. In order for it to function properly, its output frequency should not exceed 189MHz. A total of 1elements are present in it. As a result, it consumes 40μA of quiescent current without being affected by external factors. There are 20 terminations,It is powered from a supply voltage of 5V. A JK flip flop with a 4.5pFfarad input capacitance is used here. Devices in the ACTfamily are electronic devices. In this case, the maximum supply voltage (Vsup) reaches 5.5V. The supply voltage (Vsup) should be kept above 4.5V for normal operation.
74ACTQ273SJX Features
Tape & Reel (TR) package
74ACTQ series
74ACTQ273SJX Applications
There are a lot of Rochester Electronics, LLC 74ACTQ273SJX Flip Flops applications.
- Synchronous counter
- Differential Individual
- Frequency division
- Common Clocks
- Set-reset capability
- Load Control
- ATE
- Counters
- Divide a clock signal by 2 or 4
- Memory
