74AHCT374D,112
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Contact Plating | Gold |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 20-SOIC (0.295, 7.50mm Width) |
| Number of Pins | 20 |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tube |
| Published | 2008 |
| Series | 74AHCT |
| JESD-609 Code | e4 |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 20 |
| Type | D-Type |
| Technology | CMOS |
| Voltage - Supply | 4.5V~5.5V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 5V |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | 74AHCT374 |
| Function | Standard |
| Output Type | Tri-State, Non-Inverted |
| Operating Supply Voltage | 5V |
| Number of Elements | 1 |
| Polarity | Non-Inverting |
| Number of Ports | 2 |
| Number of Bits | 8 |
| Clock Frequency | 130MHz |
| Propagation Delay | 14 ns |
| Turn On Delay Time | 5.6 ns |
| Family | AHCT/VHCT |
| Logic Function | D-Type, Flip-Flop |
| Current - Quiescent (Iq) | 4μA |
| Output Characteristics | 3-STATE |
| Current - Output High, Low | 8mA 8mA |
| Max Propagation Delay @ V, Max CL | 10.4ns @ 5V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 3pF |
| Number of Input Lines | 8 |
| Clock Edge Trigger Type | Positive Edge |
| Height Seated (Max) | 2.65mm |
| Width | 7.5mm |
| Radiation Hardening | No |
| RoHS Status | ROHS3 Compliant |
74AHCT374D,112 Overview
The item is packaged in 20-SOIC (0.295, 7.50mm Width)cases. D flip flop is included in the Tubepackage. Tri-State, Non-Invertedis the output configured for it. In the configuration of the trigger, Positive Edgeis used. There is an electrical part that is mounted in the way of Surface Mount. It operates with a supply voltage of 4.5V~5.5V. In the operating environment, the temperature is -40°C~125°C TA. It belongs to the type D-Typeof flip flops. JK flip flop belongs to the 74AHCTseries of FPGAs. A frequency of 130MHzshould not be exceeded by its output. D latch consists of 1 elements. As a result, it consumes 4μA quiescent current and is not affected by external forces. 20terminations have occurred. The 74AHCT374 family contains it. An input voltage of 5Vpowers the D latch. The input capacitance of this T flip flop is 3pF farads, which is defined as the capacitance between the input terminals of an op amp with either input grounded. It is a member of the AHCT/VHCTfamily of D flip flop. In this case, the electronic component is mounted in the way of Surface Mount. With its 20pins, it is designed to work with most electronic flip flops. This device has Positive Edgeas its clock edge trigger type. It is designed with 8bits. This flip flop has a total of 2ports. Optimal efficiency requires a supply voltage of 5V. Currently, there are 8 lines of input.
74AHCT374D,112 Features
Tube package
74AHCT series
20 pins
8 Bits
74AHCT374D,112 Applications
There are a lot of Nexperia USA Inc. 74AHCT374D,112 Flip Flops applications.
- Balanced Propagation Delays
- Control circuits
- Storage registers
- Balanced 24 mA output drivers
- Circuit Design
- Buffered Clock
- Memory
- Storage Registers
- Test & Measurement
- ESD performance
