74ALVC374PW,112
| Parameters | |
|---|---|
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 20-TSSOP (0.173, 4.40mm Width) |
| Number of Pins | 20 |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tube |
| Series | 74ALVC |
| JESD-609 Code | e4 |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 20 |
| Type | D-Type |
| Terminal Finish | Nickel/Palladium/Gold (Ni/Pd/Au) |
| Technology | CMOS |
| Voltage - Supply | 1.65V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 2.7V |
| Terminal Pitch | 0.65mm |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | 74ALVC374 |
| Function | Standard |
| Output Type | Tri-State, Non-Inverted |
| Number of Elements | 1 |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 3.6V |
| Number of Ports | 2 |
| Number of Bits | 8 |
| Clock Frequency | 300MHz |
| Propagation Delay | 2.5 ns |
| Turn On Delay Time | 3.1 ns |
| Family | ALVC/VCX/A |
| Logic Function | D-Type, Flip-Flop |
| Current - Quiescent (Iq) | 10μA |
| Output Characteristics | 3-STATE |
| Current - Output High, Low | 24mA 24mA |
| Max Propagation Delay @ V, Max CL | 3.6ns @ 3.3V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 3.5pF |
| Number of Input Lines | 8 |
| Clock Edge Trigger Type | Positive Edge |
| Length | 6.5mm |
| Width | 4.4mm |
| Radiation Hardening | No |
| RoHS Status | RoHS Compliant |
74ALVC374PW,112 Overview
The package is in the form of 20-TSSOP (0.173, 4.40mm Width). There is an embedded version in the package Tube. T flip flop is configured with an output of Tri-State, Non-Inverted. This trigger is configured to use Positive Edge. In this case, the electronic component is mounted in the way of Surface Mount. The JK flip flop operates at 1.65V~3.6Vvolts. It is operating at a temperature of -40°C~85°C TA. D-Typedescribes this flip flop. It is a type of FPGA belonging to the 74ALVC series. It should not exceed 300MHzin its output frequency. A total of 1elements are present in it. T flip flop consumes 10μA quiescent energy. Terminations are 20. Members of the 74ALVC374family make up this object. Power is supplied from a voltage of 2.7V volts. The input capacitance of this JK flip flopis 3.5pF farads. It is a member of the ALVC/VCX/Afamily of D flip flop. There is an electronic component mounted in the way of Surface Mount. Basically, it is designed with a set of 20 pins. The clock edge trigger type for this device is Positive Edge. The flip flop is designed with 8bits. Vsup reaches its maximum value at 3.6V. The flip flop contains 2ports. Currently, there are 8 lines of input.
74ALVC374PW,112 Features
Tube package
74ALVC series
20 pins
8 Bits
74ALVC374PW,112 Applications
There are a lot of Nexperia USA Inc. 74ALVC374PW,112 Flip Flops applications.
- Circuit Design
- Balanced 24 mA output drivers
- Computers
- Set-reset capability
- Counters
- Single Up Count-Control Line
- Storage registers
- Synchronous counter
- ESD protection
- Supports Live Insertion
