74ALVCH16823PAG
| Parameters | |
|---|---|
| Mounting Type | Surface Mount |
| Package / Case | 56-TFSOP (0.240, 6.10mm Width) |
| Supplier Device Package | 56-TSSOP |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tube |
| Series | 74ALVCH |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Type | D-Type |
| Voltage - Supply | 2.7V~3.6V |
| Function | Master Reset |
| Output Type | Tri-State, Non-Inverted |
| Number of Elements | 1 |
| Clock Frequency | 150MHz |
| Current - Quiescent (Iq) | 40μA |
| Current - Output High, Low | 24mA 24mA |
| Number of Bits per Element | 18 |
| Trigger Type | Positive Edge |
| Input Capacitance | 5pF |
| RoHS Status | ROHS3 Compliant |
74ALVCH16823PAG Overview
The item is packaged in 56-TFSOP (0.240, 6.10mm Width)cases. Package Tubeembeds it. In the configuration, Tri-State, Non-Invertedis used as the output. This trigger uses the value Positive Edge. There is an electronic component mounted in the way of Surface Mount. A voltage of 2.7V~3.6Vis required for its operation. Temperature is set to -40°C~85°C TA. D-Typeis the type of this D latch. This type of FPGA is a part of the 74ALVCH series. A frequency of 150MHzshould be the maximum output frequency. D latch consists of 1 elements. There is a consumption of 40μAof quiescent energy. There is 5pF input capacitance for this T flip flop.
74ALVCH16823PAG Features
Tube package
74ALVCH series
74ALVCH16823PAG Applications
There are a lot of Rochester Electronics, LLC 74ALVCH16823PAG Flip Flops applications.
- Event Detectors
- Cold spare funcion
- Buffered Clock
- Computing
- Memory
- EMI reduction circuitry
- ESD protection
- Matched Rise and Fall
- Dynamic threshold performance
- High Performance Logic for test systems
