74AUP1G175GM,115
| Parameters | |
|---|---|
| Packaging | Tape & Reel (TR) |
| Series | 74AUP |
| JESD-609 Code | e3 |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 6 |
| Type | D-Type |
| Technology | CMOS |
| Voltage - Supply | 0.8V~3.6V |
| Terminal Position | DUAL |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 1.2V |
| Terminal Pitch | 0.5mm |
| Time@Peak Reflow Temperature-Max (s) | 40 |
| Base Part Number | 74AUP1G175 |
| Function | Reset |
| Output Type | Non-Inverted |
| Polarity | Non-Inverting |
| Supply Voltage-Min (Vsup) | 0.8V |
| Number of Circuits | 1 |
| Number of Bits | 1 |
| Clock Frequency | 300MHz |
| Propagation Delay | 19.5 ns |
| Quiescent Current | 500nA |
| Turn On Delay Time | 21.1 ns |
| Family | AUP/ULP/V |
| Current - Output High, Low | 4mA 4mA |
| Max Propagation Delay @ V, Max CL | 5.7ns @ 3.3V, 30pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 0.8pF |
| Clock Edge Trigger Type | Positive Edge |
| Height Seated (Max) | 0.5mm |
| Radiation Hardening | No |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
| Factory Lead Time | 1 Week |
| Contact Plating | Tin |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 6-XFDFN |
| Number of Pins | 6 |
| Operating Temperature | -40°C~125°C TA |
74AUP1G175GM,115 Overview
It is embeded in 6-XFDFN case. A package named Tape & Reel (TR)includes it. As configured, the output uses Non-Inverted. It is configured with a trigger that uses Positive Edge. This electronic part is mounted in the way of Surface Mount. A voltage of 0.8V~3.6Vis used as the supply voltage. Temperature is set to -40°C~125°C TA. D-Typeis the type of this D latch. It belongs to the 74AUPseries of FPGAs. In order for it to function properly, its output frequency should not exceed 300MHz. There have been 6 terminations. Members of the 74AUP1G175family make up this object. The D flip flop is powered by a voltage of 1.2V . The input capacitance of this JK flip flopis 0.8pF farads. In this case, the D flip flop belongs to the AUP/ULP/Vfamily. There is an electronic part mounted in the way of Surface Mount. It is designed with 6 pins. Edge triggering is a type of triggering that allows a circuit to become active at the positive edge or the negative edge of the clock signal. The clock edge trigger type of this device is Positive Edge. Flip flops designed with 1bits are used in this part. Normally, the supply voltage (Vsup) should be kept above 0.8V. The superior flexibility of this product is achieved by using 1 circuits. There is a consumption of 500nAof quiescent current from it.
74AUP1G175GM,115 Features
Tape & Reel (TR) package
74AUP series
6 pins
1 Bits
74AUP1G175GM,115 Applications
There are a lot of Nexperia USA Inc. 74AUP1G175GM,115 Flip Flops applications.
- Storage registers
- ESCC
- Event Detectors
- Individual Asynchronous Resets
- Cold spare funcion
- Bus hold
- Memory
- Differential Individual
- Reduced system switching noise
- Bounce elimination switch
