74AUP1G175GM,132
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Mounting Type | Surface Mount |
| Package / Case | 6-XFDFN |
| Surface Mount | YES |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74AUP |
| JESD-609 Code | e3 |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 6 |
| Type | D-Type |
| Terminal Finish | Tin (Sn) |
| Technology | CMOS |
| Voltage - Supply | 0.8V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | NO LEAD |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 1.2V |
| Terminal Pitch | 0.5mm |
| Time@Peak Reflow Temperature-Max (s) | 40 |
| Base Part Number | 74AUP1G175 |
| JESD-30 Code | R-PDSO-N6 |
| Function | Reset |
| Qualification Status | Not Qualified |
| Output Type | Non-Inverted |
| Number of Elements | 1 |
| Supply Voltage-Max (Vsup) | 3.6V |
| Supply Voltage-Min (Vsup) | 0.8V |
| Number of Bits | 1 |
| Clock Frequency | 300MHz |
| Family | AUP/ULP/V |
| Current - Quiescent (Iq) | 500nA |
| Current - Output High, Low | 4mA 4mA |
| Output Polarity | TRUE |
| Max Propagation Delay @ V, Max CL | 5.7ns @ 3.3V, 30pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 0.8pF |
| Height Seated (Max) | 0.5mm |
| RoHS Status | ROHS3 Compliant |
74AUP1G175GM,132 Overview
It is embeded in 6-XFDFN case. D flip flop is included in the Tape & Reel (TR)package. As configured, the output uses Non-Inverted. This trigger is configured to use Positive Edge. It is mounted in the way of Surface Mount. The JK flip flop operates with an input voltage of 0.8V~3.6V volts. It is at -40°C~125°C TAdegrees Celsius that the system is operating. D-Typedescribes this flip flop. It is a type of FPGA belonging to the 74AUP series. There should be no greater frequency than 300MHzon its output. A total of 1elements are contained within it. As a result, it consumes 500nA quiescent current. It has been determined that there have been 6 terminations. It is a member of the 74AUP1G175 family. A voltage of 1.2V provides power to the D latch. This T flip flop has a capacitance of 0.8pF farads at the input. In this case, the D flip flop belongs to the AUP/ULP/Vfamily. This flip flop is designed with 1 Bits. Vsup reaches 3.6V, the maximal supply voltage. For normal operation, the supply voltage (Vsup) should be kept above 0.8V.
74AUP1G175GM,132 Features
Tape & Reel (TR) package
74AUP series
1 Bits
74AUP1G175GM,132 Applications
There are a lot of Nexperia USA Inc. 74AUP1G175GM,132 Flip Flops applications.
- Patented noise
- Cold spare funcion
- Storage registers
- Power down protection
- Pattern generators
- Synchronous counter
- ESCC
- Control circuits
- Buffer registers
- Memory
