74AUP1G175GS,132
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 6-XFDFN |
| Number of Pins | 6 |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74AUP |
| JESD-609 Code | e3 |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 6 |
| Type | D-Type |
| Terminal Finish | Tin (Sn) |
| Technology | CMOS |
| Voltage - Supply | 0.8V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | NO LEAD |
| Peak Reflow Temperature (Cel) | NOT SPECIFIED |
| Supply Voltage | 1.1V |
| Terminal Pitch | 0.35mm |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| Base Part Number | 74AUP1G175 |
| Function | Reset |
| Output Type | Non-Inverted |
| Number of Elements | 1 |
| Supply Voltage-Min (Vsup) | 0.8V |
| Number of Bits | 1 |
| Clock Frequency | 300MHz |
| Propagation Delay | 12 ns |
| Turn On Delay Time | 21.1 ns |
| Family | AUP/ULP/V |
| Current - Quiescent (Iq) | 500nA |
| Current - Output High, Low | 4mA 4mA |
| Output Polarity | TRUE |
| Max Propagation Delay @ V, Max CL | 5.7ns @ 3.3V, 30pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 0.8pF |
| Clock Edge Trigger Type | Positive Edge |
| Height Seated (Max) | 0.35mm |
| RoHS Status | ROHS3 Compliant |
74AUP1G175GS,132 Overview
It is packaged in the way of 6-XFDFN. D flip flop is embedded in the Tape & Reel (TR) package. Non-Invertedis the output configured for it. It is configured with the trigger Positive Edge. Surface Mountis positioned in the way of this electronic part. With a supply voltage of 0.8V~3.6V volts, it operates. Temperature is set to -40°C~125°C TA. This D latch has the type D-Type. This type of FPGA is a part of the 74AUP series. Its output frequency should not exceed 300MHz. D latch consists of 1 elements. As a result, it consumes 500nA quiescent current and is not affected by external forces. 6terminations have occurred. The object belongs to the 74AUP1G175 family. Power is provided by a 1.1V supply. Its input capacitance is 0.8pFfarads. The electronic device belongs to the AUP/ULP/Vfamily. It is mounted in the way of Surface Mount. The electronic flip flop is designed with pins 6. Its clock edge trigger type is Positive Edge. Flip flops designed with 1bits are used in this part. It is imperative that the supply voltage (Vsup) is maintained above 0.8Vin order to ensure normal operation.
74AUP1G175GS,132 Features
Tape & Reel (TR) package
74AUP series
6 pins
1 Bits
74AUP1G175GS,132 Applications
There are a lot of Nexperia USA Inc. 74AUP1G175GS,132 Flip Flops applications.
- Synchronous counter
- Functionally equivalent to the MC10/100EL29
- Balanced Propagation Delays
- Cold spare funcion
- Bus hold
- Patented noise
- Data transfer
- Clock pulse
- Dynamic threshold performance
- Memory
