74AUP1G374GF,132
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Contact Plating | Tin |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 6-XFDFN |
| Number of Pins | 6 |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74AUP |
| JESD-609 Code | e3 |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 6 |
| Type | D-Type |
| Technology | CMOS |
| Voltage - Supply | 0.8V~3.6V |
| Terminal Position | DUAL |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 1.1V |
| Terminal Pitch | 0.35mm |
| Time@Peak Reflow Temperature-Max (s) | 40 |
| Base Part Number | 74AUP1G374 |
| Function | Standard |
| Output Type | Tri-State, Non-Inverted |
| Polarity | Non-Inverting |
| Supply Voltage-Min (Vsup) | 0.8V |
| Number of Circuits | 1 |
| Number of Bits | 1 |
| Clock Frequency | 309MHz |
| Propagation Delay | 20.5 ns |
| Quiescent Current | 500nA |
| Turn On Delay Time | 23.6 ns |
| Family | AUP/ULP/V |
| Output Characteristics | 3-STATE |
| Current - Output High, Low | 4mA 4mA |
| Max Propagation Delay @ V, Max CL | 5.8ns @ 3.3V, 30pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 0.8pF |
| Clock Edge Trigger Type | Positive Edge |
| Height Seated (Max) | 0.5mm |
| Radiation Hardening | No |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
74AUP1G374GF,132 Overview
It is embeded in 6-XFDFN case. D flip flop is included in the Tape & Reel (TR)package. Currently, the output is configured to use Tri-State, Non-Inverted. JK flip flop uses Positive Edgeas the trigger. There is an electronic component mounted in the way of Surface Mount. The JK flip flop operates at 0.8V~3.6Vvolts. The operating temperature is -40°C~125°C TA. This logic flip flop is classified as type D-Type. FPGAs belonging to the 74AUPseries contain this type of chip. Its output frequency should not exceed 309MHz Hz. There are 6 terminations, which are the practice of ending a transmission line with a device that matches the characteristic impedance of the line. This D latch belongs to the family of 74AUP1G374. A voltage of 1.1V is used as the power supply for this D latch. There is 0.8pF input capacitance for this T flip flop. This D flip flop belongs to the family of AUP/ULP/V. A part of the electronic system is mounted in the way of Surface Mount. There are 6pins on it. This device has Positive Edgeas its clock edge trigger type. An electronic part with 1bits has been designed. For normal operation, the supply voltage (Vsup) should be kept above 0.8V. Its superior flexibility is attributed to its use of 1 circuits. Quiescent current is consumed by the D latch in the amount of 500nA.
74AUP1G374GF,132 Features
Tape & Reel (TR) package
74AUP series
6 pins
1 Bits
74AUP1G374GF,132 Applications
There are a lot of Nexperia USA Inc. 74AUP1G374GF,132 Flip Flops applications.
- Guaranteed simultaneous switching noise level
- Safety Clamp
- Communications
- Latch
- Single Down Count-Control Line
- Load Control
- Divide a clock signal by 2 or 4
- Memory
- Reduced system switching noise
- Digital electronics systems
