74AUP1G74DC,125
| Parameters | |
|---|---|
| Trigger Type | Positive Edge |
| Input Capacitance | 0.6pF |
| Propagation Delay (tpd) | 23.3 ns |
| Length | 2.3mm |
| Width | 2mm |
| RoHS Status | ROHS3 Compliant |
| Factory Lead Time | 1 Week |
| Mounting Type | Surface Mount |
| Package / Case | 8-VFSOP (0.091, 2.30mm Width) |
| Surface Mount | YES |
| Number of Pins | 8 |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74AUP |
| JESD-609 Code | e4 |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 8 |
| Type | D-Type |
| Terminal Finish | Nickel/Palladium/Gold (Ni/Pd/Au) |
| Technology | CMOS |
| Voltage - Supply | 0.8V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 1.2V |
| Terminal Pitch | 0.5mm |
| Time@Peak Reflow Temperature-Max (s) | 40 |
| Base Part Number | 74AUP1G74 |
| Function | Set(Preset) and Reset |
| Qualification Status | Not Qualified |
| Output Type | Differential |
| Number of Elements | 1 |
| Supply Voltage-Max (Vsup) | 3.6V |
| Output Current | 20mA |
| Number of Bits | 1 |
| Clock Frequency | 315MHz |
| Family | AUP/ULP/V |
| Current - Quiescent (Iq) | 500nA |
| Current - Output High, Low | 4mA 4mA |
| Output Polarity | COMPLEMENTARY |
| Max Propagation Delay @ V, Max CL | 5.8ns @ 3.3V, 30pF |
74AUP1G74DC,125 Overview
It is packaged in the way of 8-VFSOP (0.091, 2.30mm Width). Package Tape & Reel (TR)embeds it. This output is configured with Differential. The trigger it is configured with uses Positive Edge. Surface Mountis in the way of this electric part. The supply voltage is set to 0.8V~3.6V. In this case, the operating temperature is -40°C~125°C TA. Logic flip flops of this type are classified as D-Type. JK flip flop belongs to the 74AUPseries of FPGAs. In order for it to function properly, its output frequency should not exceed 315MHz. A total of 1 elements are present. As a result, it consumes 500nA of quiescent current without being affected by external factors. A total of 8terminations have been recorded. JK flip flop belongs to 74AUP1G74 family. Power is supplied from a voltage of 1.2V volts. The input capacitance of this JK flip flopis 0.6pF farads. The electronic device belongs to the AUP/ULP/Vfamily. 8pins are included in its design. This flip flop is designed with 1 Bits. It reaches 3.6Vwhen the supply voltage is maximal (Vsup). It offers maximum design flexibility with its output current of 20mA.
74AUP1G74DC,125 Features
Tape & Reel (TR) package
74AUP series
8 pins
1 Bits
74AUP1G74DC,125 Applications
There are a lot of Nexperia USA Inc. 74AUP1G74DC,125 Flip Flops applications.
- Bus hold
- ESCC
- Pattern generators
- ESD performance
- Test & Measurement
- Common Clocks
- Data Synchronizers
- Shift Registers
- Dynamic threshold performance
- Circuit Design
