74AUP1G74GN,115
| Parameters | |
|---|---|
| Number of Bits | 1 |
| Clock Frequency | 315MHz |
| Propagation Delay | 14.2 ns |
| Quiescent Current | 500nA |
| Turn On Delay Time | 2.2 ns |
| Family | AUP/ULP/V |
| Logic Function | AND, D-Type |
| Current - Output High, Low | 4mA 4mA |
| Max Propagation Delay @ V, Max CL | 5.8ns @ 3.3V, 30pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 0.6pF |
| Clock Edge Trigger Type | Positive Edge |
| Height Seated (Max) | 0.35mm |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
| Factory Lead Time | 1 Week |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 8-XFDFN |
| Number of Pins | 8 |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74AUP |
| JESD-609 Code | e3 |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 8 |
| Type | D-Type |
| Terminal Finish | Tin (Sn) |
| Technology | CMOS |
| Voltage - Supply | 0.8V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | NO LEAD |
| Peak Reflow Temperature (Cel) | NOT SPECIFIED |
| Supply Voltage | 1.1V |
| Terminal Pitch | 0.3mm |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| Base Part Number | 74AUP1G74 |
| Function | Set(Preset) and Reset |
| Output Type | Differential |
| Number of Elements | 1 |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 3.6V |
74AUP1G74GN,115 Overview
As a result, it is packaged as 8-XFDFN. D flip flop is included in the Tape & Reel (TR)package. The output it is configured with uses Differential. There is a trigger configured with Positive Edge. The electronic part is mounted in the way of Surface Mount. The JK flip flop operates with an input voltage of 0.8V~3.6V volts. It is operating at -40°C~125°C TA. It belongs to the type D-Typeof flip flops. FPGAs belonging to the 74AUPseries contain this type of chip. You should not exceed 315MHzin its output frequency. The element count is 1 . A total of 8 terminations have been made. The 74AUP1G74family includes it. A voltage of 1.1V is used to power it. The input capacitance of this JK flip flopis 0.6pF farads. AUP/ULP/Vis the family of this D flip flop. It is mounted by the way of Surface Mount. This board has 8 pins. This device has Positive Edgeas its clock edge trigger type. The flip flop is designed with 1bits. In this case, the maximum supply voltage (Vsup) reaches 3.6V. There is a consumption of 500nAof quiescent current from it.
74AUP1G74GN,115 Features
Tape & Reel (TR) package
74AUP series
8 pins
1 Bits
74AUP1G74GN,115 Applications
There are a lot of Nexperia USA Inc. 74AUP1G74GN,115 Flip Flops applications.
- Frequency Dividers
- Guaranteed simultaneous switching noise level
- QML qualified product
- ATE
- Load Control
- Storage registers
- Bus hold
- Common Clocks
- Divide a clock signal by 2 or 4
- Data transfer
