74AUP1G74GT,115
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Contact Plating | Tin |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 8-XFDFN |
| Number of Pins | 8 |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74AUP |
| JESD-609 Code | e3 |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 8 |
| Type | D-Type |
| Technology | CMOS |
| Voltage - Supply | 0.8V~3.6V |
| Terminal Position | DUAL |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 1.2V |
| Terminal Pitch | 0.5mm |
| Time@Peak Reflow Temperature-Max (s) | 40 |
| Base Part Number | 74AUP1G74 |
| Function | Set(Preset) and Reset |
| Output Type | Differential |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 3.6V |
| Number of Circuits | 1 |
| Number of Bits | 1 |
| Clock Frequency | 315MHz |
| Propagation Delay | 22.5 ns |
| Quiescent Current | 500nA |
| Turn On Delay Time | 2.2 ns |
| Family | AUP/ULP/V |
| Logic Function | AND, D-Type |
| Current - Output High, Low | 4mA 4mA |
| Max Propagation Delay @ V, Max CL | 5.8ns @ 3.3V, 30pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 0.6pF |
| Clock Edge Trigger Type | Positive Edge |
| Height Seated (Max) | 0.5mm |
| Radiation Hardening | No |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
74AUP1G74GT,115 Overview
It is embeded in 8-XFDFN case. As part of the package Tape & Reel (TR), it is embedded. T flip flop uses Differentialas the output. It is configured with the trigger Positive Edge. The electronic part is mounted in the way of Surface Mount. With a supply voltage of 0.8V~3.6V volts, it operates. In the operating environment, the temperature is -40°C~125°C TA. It belongs to the type D-Typeof flip flops. In FPGA terms, D flip flop is a type of 74AUPseries FPGA. In order for it to function properly, its output frequency should not exceed 315MHz. A total of 8 terminations have been made. The object belongs to the 74AUP1G74 family. It is powered from a supply voltage of 1.2V. There is 0.6pF input capacitance for this T flip flop. The electronic device belongs to the AUP/ULP/Vfamily. A part of the electronic system is mounted in the way of Surface Mount. A total of 8pins are provided on this board. The clock edge trigger type for this device is Positive Edge. It is designed with a number of bits of 1. There is a 3.6Vmaximum supply voltage (Vsup). The superior flexibility is achieved through the use of 1 circuits. 500nAquiescent current consumed.
74AUP1G74GT,115 Features
Tape & Reel (TR) package
74AUP series
8 pins
1 Bits
74AUP1G74GT,115 Applications
There are a lot of Nexperia USA Inc. 74AUP1G74GT,115 Flip Flops applications.
- Modulo – n – counter
- EMI reduction circuitry
- ESD protection
- Registers
- Power down protection
- Bus hold
- Automotive
- Single Down Count-Control Line
- Consumer
- Reduced system switching noise
