74AUP1G79GF,132
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Contact Plating | Tin |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 6-XFDFN |
| Number of Pins | 6 |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74AUP |
| JESD-609 Code | e3 |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 6 |
| Type | D-Type |
| Technology | CMOS |
| Voltage - Supply | 0.8V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | NO LEAD |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 1.1V |
| Terminal Pitch | 0.35mm |
| Time@Peak Reflow Temperature-Max (s) | 40 |
| Base Part Number | 74AUP1G79 |
| Function | Standard |
| Qualification Status | Not Qualified |
| Output Type | Non-Inverted |
| Polarity | Non-Inverting |
| Supply Voltage-Min (Vsup) | 0.8V |
| Number of Circuits | 1 |
| Number of Bits | 1 |
| Clock Frequency | 309MHz |
| Propagation Delay | 17.3 ns |
| Quiescent Current | 500nA |
| Turn On Delay Time | 2 ns |
| Family | AUP/ULP/V |
| Current - Output High, Low | 4mA 4mA |
| Max Propagation Delay @ V, Max CL | 5.8ns @ 3.3V, 30pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 0.8pF |
| Clock Edge Trigger Type | Positive Edge |
| Height Seated (Max) | 0.5mm |
| RoHS Status | ROHS3 Compliant |
74AUP1G79GF,132 Overview
As a result, it is packaged as 6-XFDFN. You can find it in the Tape & Reel (TR)package. In the configuration, Non-Invertedis used as the output. JK flip flop uses Positive Edgeas the trigger. There is an electronic component mounted in the way of Surface Mount. A voltage of 0.8V~3.6Vis used as the supply voltage. A temperature of -40°C~125°C TAis considered to be the operating temperature. It is an electronic flip flop with the type D-Type. The 74AUPseries comprises this type of FPGA. Its output frequency should not exceed 309MHz Hz. There are 6 terminations, which are the practice of ending a transmission line with a device that matches the characteristic impedance of the line. It is a member of the 74AUP1G79 family. A voltage of 1.1V provides power to the D latch. Input capacitance of this device is 0.8pF farads. Devices in the AUP/ULP/Vfamily are electronic devices. The electronic part is mounted in the way of Surface Mount. Basically, it is designed with a set of 6 pins. This device has Positive Edgeas its clock edge trigger type. 1bits are used in its design. For normal operation, the supply voltage (Vsup) should be kept above 0.8V. The superior flexibility of this circuit is achieved by using 1 circuits. In terms of quiescent current, it consumes 500nA .
74AUP1G79GF,132 Features
Tape & Reel (TR) package
74AUP series
6 pins
1 Bits
74AUP1G79GF,132 Applications
There are a lot of Nexperia USA Inc. 74AUP1G79GF,132 Flip Flops applications.
- ESD protection
- Single Up Count-Control Line
- EMI reduction circuitry
- Digital electronics systems
- Latch
- Shift Registers
- Frequency Dividers
- Single Down Count-Control Line
- Supports Live Insertion
- Divide a clock signal by 2 or 4
