74AUP1G79GN,132
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Contact Plating | Tin |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 6-XFDFN |
| Number of Pins | 6 |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74AUP |
| JESD-609 Code | e3 |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 6 |
| Type | D-Type |
| Technology | CMOS |
| Voltage - Supply | 0.8V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | NO LEAD |
| Peak Reflow Temperature (Cel) | NOT SPECIFIED |
| Supply Voltage | 1.1V |
| Terminal Pitch | 0.3mm |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| Base Part Number | 74AUP1G79 |
| Function | Standard |
| Output Type | Non-Inverted |
| Number of Elements | 1 |
| Polarity | Non-Inverting |
| Supply Voltage-Min (Vsup) | 0.8V |
| Number of Bits | 1 |
| Clock Frequency | 309MHz |
| Propagation Delay | 14.2 ns |
| Quiescent Current | 500nA |
| Turn On Delay Time | 2 ns |
| Family | AUP/ULP/V |
| Current - Output High, Low | 4mA 4mA |
| Max Propagation Delay @ V, Max CL | 5.8ns @ 3.3V, 30pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 0.8pF |
| Clock Edge Trigger Type | Positive Edge |
| Height Seated (Max) | 0.35mm |
| Width | 0.9mm |
| RoHS Status | ROHS3 Compliant |
74AUP1G79GN,132 Overview
It is packaged in the way of 6-XFDFN. You can find it in the Tape & Reel (TR)package. T flip flop uses Non-Invertedas its output configuration. There is a trigger configured with Positive Edge. Surface Mountis positioned in the way of this electronic part. A voltage of 0.8V~3.6Vis used as the supply voltage. In the operating environment, the temperature is -40°C~125°C TA. It belongs to the type D-Typeof flip flops. The 74AUPseries comprises this type of FPGA. Its output frequency should not exceed 309MHz Hz. There are 1 elements in it. It has been determined that there have been 6 terminations. The 74AUP1G79 family contains it. A voltage of 1.1V is used as the power supply for this D latch. Input capacitance of this device is 0.8pF farads. The electronic device belongs to the AUP/ULP/Vfamily. There is an electronic part that is mounted in the way of Surface Mount. 6pins are included in its design. It has a clock edge trigger type of Positive Edge. There are 1bits in this flip flop. The supply voltage (Vsup) should be maintained above 0.8V for normal operation. Quiescent current is consumed by the D latch in the amount of 500nA.
74AUP1G79GN,132 Features
Tape & Reel (TR) package
74AUP series
6 pins
1 Bits
74AUP1G79GN,132 Applications
There are a lot of Nexperia USA Inc. 74AUP1G79GN,132 Flip Flops applications.
- Functionally equivalent to the MC10/100EL29
- 2 – Bit synchronous counter
- QML qualified product
- Bus hold
- ESD performance
- Single Up Count-Control Line
- Load Control
- Data transfer
- Circuit Design
- Latch-up performance
