74AUP1G79GV,125
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Contact Plating | Tin |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | SC-74A, SOT-753 |
| Number of Pins | 5 |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74AUP |
| JESD-609 Code | e3 |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 5 |
| Type | D-Type |
| Technology | CMOS |
| Voltage - Supply | 0.8V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Supply Voltage | 1.1V |
| Base Part Number | 74AUP1G79 |
| Function | Standard |
| Output Type | Non-Inverted |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 3.6V |
| Supply Voltage-Min (Vsup) | 0.8V |
| Number of Circuits | 1 |
| Output Current | 20mA |
| Number of Bits | 1 |
| Clock Frequency | 309MHz |
| Propagation Delay | 25.6 ns |
| Quiescent Current | 500nA |
| Turn On Delay Time | 2 ns |
| Family | AUP/ULP/V |
| Logic Function | D-Type, Flip-Flop |
| Current - Output High, Low | 4mA 4mA |
| Max Propagation Delay @ V, Max CL | 5.8ns @ 3.3V, 30pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 0.8pF |
| Clock Edge Trigger Type | Positive Edge |
| Length | 2.9mm |
| Radiation Hardening | No |
| REACH SVHC | No SVHC |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
74AUP1G79GV,125 Overview
The package is in the form of SC-74A, SOT-753. Package Tape & Reel (TR)embeds it. There is a Non-Invertedoutput configured with it. In the configuration of the trigger, Positive Edgeis used. This electronic part is mounted in the way of Surface Mount. The JK flip flop operates at 0.8V~3.6Vvolts. The operating temperature is -40°C~125°C TA. The type of this D latch is D-Type. It belongs to the 74AUPseries of FPGAs. A frequency of 309MHzshould not be exceeded by its output. A total of 5terminations have been recorded. You can search similar parts based on 74AUP1G79. A voltage of 1.1V provides power to the D latch. Its input capacitance is 0.8pF farads. It is a member of the AUP/ULP/Vfamily of D flip flop. There is an electronic component mounted in the way of Surface Mount. 5pins are included in its design. This device exhibits a clock edge trigger type of Positive Edge. It is designed with 1bits. It reaches 3.6Vwhen the maximum supply voltage (Vsup) is applied. For normal operation, the supply voltage (Vsup) should be above 0.8V. To achieve this superior flexibility, 1 circuits are used. In addition to its maximum design flexibility, the output current of the T flip flop is 20mA. This D latch consumes 500nA quiescent current at all.
74AUP1G79GV,125 Features
Tape & Reel (TR) package
74AUP series
5 pins
1 Bits
74AUP1G79GV,125 Applications
There are a lot of Nexperia USA Inc. 74AUP1G79GV,125 Flip Flops applications.
- Frequency Divider circuits
- Latch
- Memory
- Single Down Count-Control Line
- Set-reset capability
- QML qualified product
- Differential Individual
- Individual Asynchronous Resets
- 2 – Bit synchronous counter
- Frequency division
