74AUP1G80GM,115
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Contact Plating | Tin |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 6-XFDFN |
| Number of Pins | 6 |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74AUP |
| JESD-609 Code | e3 |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 6 |
| Type | D-Type |
| Technology | CMOS |
| Voltage - Supply | 0.8V~3.6V |
| Terminal Position | DUAL |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 1.2V |
| Terminal Pitch | 0.5mm |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | 74AUP1G80 |
| Function | Standard |
| Output Type | Inverted |
| Polarity | Inverting |
| Supply Voltage-Min (Vsup) | 0.8V |
| Number of Circuits | 1 |
| Number of Bits | 1 |
| Clock Frequency | 309MHz |
| Propagation Delay | 20.7 ns |
| Quiescent Current | 500nA |
| Turn On Delay Time | 2.2 ns |
| Family | AUP/ULP/V |
| Current - Output High, Low | 4mA 4mA |
| Max Propagation Delay @ V, Max CL | 6.4ns @ 3.3V, 30pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 1.5pF |
| Clock Edge Trigger Type | Positive Edge |
| Height Seated (Max) | 0.5mm |
| Radiation Hardening | No |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
74AUP1G80GM,115 Overview
The item is packaged in 6-XFDFNcases. You can find it in the Tape & Reel (TR)package. T flip flop is configured with an output of Inverted. JK flip flop uses Positive Edgeas the trigger. There is an electrical part that is mounted in the way of Surface Mount. The supply voltage is set to 0.8V~3.6V. A temperature of -40°C~125°C TAis used in the operation. The type of this D latch is D-Type. In this case, it is a type of FPGA belonging to the 74AUP series. There should be no greater frequency than 309MHzon its output. Currently, there are 6 terminations. This D latch belongs to the family of 74AUP1G80. A voltage of 1.2V provides power to the D latch. JK flip flop input capacitance is 1.5pF farads. Devices in the AUP/ULP/Vfamily are electronic devices. This electronic part is mounted in the way of Surface Mount. The electronic flip flop is designed with pins 6. Edge triggering is a type of triggering that allows a circuit to become active at the positive edge or the negative edge of the clock signal. The clock edge trigger type of this device is Positive Edge. The flip flop is designed with 1bits. Normally, the supply voltage (Vsup) should be kept above 0.8V. The superior flexibility is achieved through the use of 1 circuits. This D latch consumes 500nA quiescent current at all.
74AUP1G80GM,115 Features
Tape & Reel (TR) package
74AUP series
6 pins
1 Bits
74AUP1G80GM,115 Applications
There are a lot of Nexperia USA Inc. 74AUP1G80GM,115 Flip Flops applications.
- Latch
- Cold spare funcion
- Event Detectors
- EMI reduction circuitry
- Digital electronics systems
- Matched Rise and Fall
- Test & Measurement
- Clock pulse
- Counters
- Automotive
