74AUP1G80GN,132
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 6-XFDFN |
| Number of Pins | 6 |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74AUP |
| JESD-609 Code | e3 |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 6 |
| Type | D-Type |
| Terminal Finish | Tin (Sn) |
| Technology | CMOS |
| Voltage - Supply | 0.8V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | NO LEAD |
| Peak Reflow Temperature (Cel) | NOT SPECIFIED |
| Supply Voltage | 1.1V |
| Terminal Pitch | 0.3mm |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| Base Part Number | 74AUP1G80 |
| Function | Standard |
| Output Type | Inverted |
| Number of Elements | 1 |
| Supply Voltage-Min (Vsup) | 0.8V |
| Number of Bits | 1 |
| Clock Frequency | 309MHz |
| Propagation Delay | 15.7 ns |
| Turn On Delay Time | 2.2 ns |
| Family | AUP/ULP/V |
| Current - Quiescent (Iq) | 500nA |
| Current - Output High, Low | 4mA 4mA |
| Max Propagation Delay @ V, Max CL | 6.4ns @ 3.3V, 30pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 1.5pF |
| Clock Edge Trigger Type | Positive Edge |
| Height Seated (Max) | 0.35mm |
| Width | 0.9mm |
| RoHS Status | ROHS3 Compliant |
74AUP1G80GN,132 Overview
6-XFDFNis the packaging method. A package named Tape & Reel (TR)includes it. Currently, the output is configured to use Inverted. It is configured with a trigger that uses a value of Positive Edge. Surface Mountmounts this electrical part. Powered by a 0.8V~3.6Vvolt supply, it operates as follows. In this case, the operating temperature is -40°C~125°C TA. This D latch has the type D-Type. It is a type of FPGA belonging to the 74AUP series. You should not exceed 309MHzin its output frequency. A total of 1elements are contained within it. As a result, it consumes 500nA of quiescent current without being affected by external factors. In 6terminations, a transmission line is terminated with a JK flip flop that matches its characteristic impedance. Members of the 74AUP1G80family make up this object. Power is supplied from a voltage of 1.1V volts. Its input capacitance is 1.5pF farads. It belongs to the family of electronic devices known as AUP/ULP/V. In this case, the electronic component is mounted in the way of Surface Mount. A total of 6pins are provided on this board. A Positive Edgeclock edge trigger is used in this device. It is designed with 1bits. Keeping the supply voltage (Vsup) above 0.8V is necessary for normal operation.
74AUP1G80GN,132 Features
Tape & Reel (TR) package
74AUP series
6 pins
1 Bits
74AUP1G80GN,132 Applications
There are a lot of Nexperia USA Inc. 74AUP1G80GN,132 Flip Flops applications.
- Frequency Divider circuits
- Communications
- EMI reduction circuitry
- Shift registers
- Clock pulse
- ATE
- Differential Individual
- Memory
- Reduced system switching noise
- Test & Measurement
