74AUP2G79GF,115
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Contact Plating | Tin |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 8-XFDFN |
| Number of Pins | 8 |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tape & Reel (TR) |
| Published | 2010 |
| Series | 74AUP |
| JESD-609 Code | e3 |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 8 |
| Type | D-Type |
| Technology | CMOS |
| Voltage - Supply | 0.8V~3.6V |
| Terminal Position | DUAL |
| Supply Voltage | 1.1V |
| Terminal Pitch | 0.35mm |
| Base Part Number | 74AUP2G79 |
| Function | Standard |
| Output Type | Non-Inverted |
| Number of Elements | 2 |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 3.6V |
| Clock Frequency | 309MHz |
| Propagation Delay | 25.6 ns |
| Turn On Delay Time | 2 ns |
| Family | AUP/ULP/V |
| Current - Quiescent (Iq) | 500nA |
| Current - Output High, Low | 4mA 4mA |
| Number of Bits per Element | 1 |
| Max Propagation Delay @ V, Max CL | 5.8ns @ 3.3V, 30pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 0.6pF |
| Clock Edge Trigger Type | Positive Edge |
| Height Seated (Max) | 0.5mm |
| Radiation Hardening | No |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
74AUP2G79GF,115 Overview
The item is packaged in 8-XFDFNcases. The Tape & Reel (TR)package contains it. In the configuration, Non-Invertedis used as the output. This trigger uses the value Positive Edge. This electronic part is mounted in the way of Surface Mount. It operates with a supply voltage of 0.8V~3.6V. It is operating at -40°C~125°C TA. It is an electronic flip flop with the type D-Type. This type of FPGA is a part of the 74AUP series. A frequency of 309MHzshould not be exceeded by its output. There are 2 elements in it. It consumes 500nA of quiescent In 8terminations, a transmission line is terminated with a JK flip flop that matches its characteristic impedance. The 74AUP2G79family includes it. The power supply voltage is 1.1V. A JK flip flop with a 0.6pFfarad input capacitance is used here. AUP/ULP/Vis the family of this D flip flop. There is an electronic part that is mounted in the way of Surface Mount. With its 8pins, it is designed to work with most electronic flip flops. This device's clock edge trigger type is Positive Edge. 3.6Vis the maximum supply voltage (Vsup).
74AUP2G79GF,115 Features
Tape & Reel (TR) package
74AUP series
8 pins
74AUP2G79GF,115 Applications
There are a lot of Nexperia USA Inc. 74AUP2G79GF,115 Flip Flops applications.
- Differential Individual
- Pattern generators
- Guaranteed simultaneous switching noise level
- Cold spare funcion
- Computing
- Safety Clamp
- Memory
- Data storage
- Count Modes
- Patented noise
