74AUP2G79GM,125
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Contact Plating | Gold |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 8-XFQFN Exposed Pad |
| Number of Pins | 8 |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tape & Reel (TR) |
| Published | 2010 |
| Series | 74AUP |
| JESD-609 Code | e4 |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 8 |
| Type | D-Type |
| Technology | CMOS |
| Voltage - Supply | 0.8V~3.6V |
| Terminal Position | QUAD |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 1.1V |
| Terminal Pitch | 0.5mm |
| Time@Peak Reflow Temperature-Max (s) | 40 |
| Base Part Number | 74AUP2G79 |
| Function | Standard |
| Output Type | Non-Inverted |
| Number of Elements | 2 |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 3.6V |
| Number of Bits | 1 |
| Clock Frequency | 309MHz |
| Propagation Delay | 17.3 ns |
| Turn On Delay Time | 2 ns |
| Family | AUP/ULP/V |
| Logic Function | D-Type, Flip-Flop |
| Current - Quiescent (Iq) | 500nA |
| Current - Output High, Low | 4mA 4mA |
| Max Propagation Delay @ V, Max CL | 5.8ns @ 3.3V, 30pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 0.6pF |
| Number of Output Lines | 1 |
| Clock Edge Trigger Type | Positive Edge |
| Height Seated (Max) | 0.5mm |
| Radiation Hardening | No |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
74AUP2G79GM,125 Overview
It is embeded in 8-XFQFN Exposed Pad case. D flip flop is embedded in the Tape & Reel (TR) package. It is configured with Non-Invertedas an output. This trigger is configured to use Positive Edge. In this case, the electronic component is mounted in the way of Surface Mount. A 0.8V~3.6Vsupply voltage is required for it to operate. A temperature of -40°C~125°C TAis used in the operation. This electronic flip flop is of type D-Type. JK flip flop is a part of the 74AUPseries of FPGAs. In order for it to function properly, its output frequency should not exceed 309MHz. The element count is 2 . As a result, it consumes 500nA of quiescent current without being affected by external factors. It has been determined that there have been 8 terminations. The 74AUP2G79 family contains this object. A voltage of 1.1V provides power to the D latch. A 0.6pFfarad input capacitance is provided by this T flip flop. The electronic device belongs to the AUP/ULP/Vfamily. There is an electronic part mounted in the way of Surface Mount. With its 8pins, it is designed to work with most electronic flip flops. Edge triggering is a type of triggering that allows a circuit to become active at the positive edge or the negative edge of the clock signal. The clock edge trigger type of this device is Positive Edge. An electronic part with 1bits has been designed. It reaches 3.6Vwhen the maximum supply voltage (Vsup) is applied. The JK flip flop is with 1 output lines to operate.
74AUP2G79GM,125 Features
Tape & Reel (TR) package
74AUP series
8 pins
1 Bits
74AUP2G79GM,125 Applications
There are a lot of Nexperia USA Inc. 74AUP2G79GM,125 Flip Flops applications.
- Bounce elimination switch
- Circuit Design
- Automotive
- Convert a momentary switch to a toggle switch
- Computers
- Buffered Clock
- CMOS Process
- Power down protection
- High Performance Logic for test systems
- Frequency Divider circuits
