74AUP2G79GN,115
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 8-XFDFN |
| Number of Pins | 8 |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tape & Reel (TR) |
| Published | 2010 |
| Series | 74AUP |
| JESD-609 Code | e3 |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 8 |
| Type | D-Type |
| Terminal Finish | Tin (Sn) |
| Technology | CMOS |
| Voltage - Supply | 0.8V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | NO LEAD |
| Peak Reflow Temperature (Cel) | NOT SPECIFIED |
| Supply Voltage | 1.1V |
| Terminal Pitch | 0.3mm |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| Base Part Number | 74AUP2G79 |
| Function | Standard |
| Output Type | Non-Inverted |
| Number of Elements | 2 |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 3.6V |
| Clock Frequency | 309MHz |
| Propagation Delay | 25.6 ns |
| Turn On Delay Time | 2 ns |
| Family | AUP/ULP/V |
| Current - Quiescent (Iq) | 500nA |
| Current - Output High, Low | 4mA 4mA |
| Number of Bits per Element | 1 |
| Max Propagation Delay @ V, Max CL | 5.8ns @ 3.3V, 30pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 0.6pF |
| Clock Edge Trigger Type | Positive Edge |
| Height Seated (Max) | 0.35mm |
| RoHS Status | ROHS3 Compliant |
74AUP2G79GN,115 Overview
It is embeded in 8-XFDFN case. It is contained within the Tape & Reel (TR)package. In the configuration, Non-Invertedis used as the output. Positive Edgeis the trigger it is configured with. Surface Mountis positioned in the way of this electronic part. The JK flip flop operates at 0.8V~3.6Vvolts. A temperature of -40°C~125°C TAis used in the operation. This electronic flip flop is of type D-Type. In FPGA terms, D flip flop is a type of 74AUPseries FPGA. You should not exceed 309MHzin the output frequency of the device. A total of 2elements are contained within it. Despite external influences, it consumes 500nAof quiescent current. There have been 8 terminations. The 74AUP2G79family includes it. It is powered from a supply voltage of 1.1V. JK flip flop input capacitance is 0.6pF farads. In terms of electronic devices, this device belongs to the AUP/ULP/Vfamily of devices. There is an electronic component mounted in the way of Surface Mount. As you can see from the design, it has pins with 8. This device exhibits a clock edge trigger type of Positive Edge. There is a 3.6Vmaximum supply voltage (Vsup).
74AUP2G79GN,115 Features
Tape & Reel (TR) package
74AUP series
8 pins
74AUP2G79GN,115 Applications
There are a lot of Nexperia USA Inc. 74AUP2G79GN,115 Flip Flops applications.
- Digital electronics systems
- Circuit Design
- Safety Clamp
- Shift Registers
- EMI reduction circuitry
- QML qualified product
- Differential Individual
- Guaranteed simultaneous switching noise level
- Test & Measurement
- Registers
